Tor Aamodt is a Professor in the Department of Electrical and Computer Engineering at the University of British Columbia where he has been a faculty member since 2006. His current research focuses on the architecture of general-purpose graphics processor units (GPUs) and energy efficient computing including most recently, accelerators for machine learning. Along with students in his research group he developed the widely used GPGPU-Sim simulator. Three of his papers have been selected as "Top Picks" by IEEE Micro Magazine for their novelty and potential long term impact, a forth was selected as a "Top Picks" honorable mention. One of his papers was also selected as a "Research Highlight" in Communications of the ACM magazine. He is in the MICRO Hall of Fame and Program Co-Chair for MICRO 2019. He is a member of the NSERC Discovery Grant Evaluation Group for 2018 to 2020. He served as an Associate Editor for IEEE Computer Architecture Letters from 2012-2015 and the International Journal of High Performance Computing Applications from 2012-2016, was Program Chair for ISPASS 2013, General Chair for ISPASS 2014, and has served on numerous program committees. He delivered a keynote address at SAMOS 2014. He was a Visiting Associate Professor in the Computer Science Department at Stanford University during 2012-2013. He was awarded an NVIDIA Academic Partnership Award in 2010, a NSERC Discovery Accelerator for 2016-2019 and a 2016 Google Faculty Research Award (the first at UBC since 2012). He is a member of the recently funded COHESA NSERC Strategic Network studying the interactions of machine learning and hardware design. He is also a member of CAIDA: UBC ICICS Centre for Artificial Intelligence Decision-making and Action and Quantum BC. He has served as an expert in patent litigation related to GPUs and is presently consulting part-time with Huawei.

Tor received his BASc (in Engineering Science), MASc and PhD at the University of Toronto. Much of his PhD work was done while he was an intern at Intel's Microarchitecture Research Lab. Subsequently, he worked at NVIDIA on the memory system architecture ("framebuffer") of GeForce 8 Series GPU -- the first NVIDIA GPU to support CUDA.

Tor is a Professional Engineer in the province of British Columbia (registered with APEGBC).

Service

Program Chair: ISPASS 2013, MICRO 2019
General Chair: ISPASS 2014

Program Committee member: IEEE Micro Top Picks (2013, 2014, 2016, 2017 issue), ISCA (2013, 2016, 2018), MICRO (2010, 2011, 2012, 2015), HPCA (2012, 2013, 2016), HiPEAC (2012, 2013), HotPar (2013), ICS (2011, 2012), ISPASS (2009, 2010, 2011, 2012, 2018), IISWC (2010, 2011, 2012), IPDPS (2012, 2013), ICPP (2010), GLSVLSI (2010, 2011), and others.

External Program Commitee member: ISCA (2015, 2017, 2019); MICRO (2016)

CV

CV (in UBC format; chronically outdated)