Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement

TitleDefect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement
Publication TypeConference Paper
Year of Publication2005
AuthorsYu, A. J., and G. Lemieux
Conference NameField Programmable Logic and Applications, 2005. International Conference on
Pagination255 - 262
Date Publishedaug.
Keywordsdistributed interconnect defects, fault tolerance, field programmable gate arrays, fine-grain redundancy, FPGA connection block, FPGA switch block, integrated circuit interconnections, integrated circuit reliability, integrated circuit yield, interconnect defect tolerance, island-style FPGA, multiple random interconnect defects, network routing, open faults, redundancy, routing architecture, stuck-at faults, wiring tracks, yield enhancement

Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate multiple defects (Campregher et al., 2005). We propose a number of changes to the detailed routing architecture of island-style FPGAs to tolerate multiple random, distributed interconnect defects without re-routing and with minimal impact on signal timing. Our scheme is a user option prebuilt into an architecture, requiring +11% area for additional multiplexers. Unused (spare) wiring tracks are also needed, bringing total overhead to 24% to tolerate stuck-at or open faults, or 34% to include bridging. User circuits that do not fully stress the routing network already have these tracks freely available. The delay penalty is programmable: 5-10% if defect rates are expected to be sufficiently low, but can be as high as 25% if defect rates are high. Our schemes can tolerate more than 10 interconnect defects for large array sizes of 128 times; 128. Unlike row/column redundancy schemes, our schemes are scalable: they naturally tolerate more defects as the FPGA array size increases. This work is the first detailed analysis of fine-grained defect-tolerant schemes in FPGAs.


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