A minimal hardware overhead BIST data compaction scheme

TitleA minimal hardware overhead BIST data compaction scheme
Publication TypeConference Paper
Year of Publication1992
AuthorsWu, Y., and A. Ivanov
Conference NameASIC Conference and Exhibit, 1992., Proceedings of 5th Annual IEEE International
Pagination368 -371
Date Publishedsep.
Keywordsbinary sequences, BIST, built-in self test, built-in self-test, data compaction scheme, data compression, fault-free output sequences, integrated circuit testing, linear feedback shift register, logic testing, minimal hardware overhead, multiple signatures, reference-signatures, shift registers

Existing data compaction schemes for built-in self-test (BIST) usually impose substantial hardware overhead. A minimal hardware overhead data compaction scheme is proposed that can achieve reasonably small aliasing with a hardware requirement as low as a one-stage linear feedback shift register (LFSR). Multiple signatures are checked, and all reference-signatures are made identical resulting in simple circuitry for checking the signatures. The proposed scheme is based on a simple manipulation of the fault-free output sequences from the circuit under test


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