An encoder for a 5GS/s 4-bit flash ADC in 0.18/spl mu/m CMOS

TitleAn encoder for a 5GS/s 4-bit flash ADC in 0.18/spl mu/m CMOS
Publication TypeConference Paper
Year of Publication2005
AuthorsSheikhaei, S., S. Mirabbasi, and A. Ivanov
Conference NameElectrical and Computer Engineering, 2005. Canadian Conference on
Pagination698 -701
Date Publishedmay.
Keywords0.18 micron, 1.8 V, 2-stage pipelining, 4 bit, 4 mW, 5 GHz, analog-to-digital converter, analogue-digital conversion, CMOS logic circuits, CMOS technology, current mode logic, current-mode logic, encoding, high-speed encoder, low-swing signaling, speed performance enhancement

In this paper, a high-speed encoder intended for a 5GS/S 4-bit flash analog-to-digital converter (ADC) is presented. To meet the speed and power targets of the ADC, low-swing signaling is used in all the internal sub-blocks of the ADC including the encoder. To further enhance the speed performance of the encoder, 2-stage pipelining is utilized. In addition, the encoder is implemented in current mode logic (CML). The circuit is designed and simulated in a 0.18 mum CMOS technology. It consumes 4 mW from a 1.8 V supply while operating at 5 GHz


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