A 4-bit 5 GS/s flash A/D converter in 0.18 mu;m CMOS

TitleA 4-bit 5 GS/s flash A/D converter in 0.18 mu;m CMOS
Publication TypeConference Paper
Year of Publication2005
AuthorsSheikhaei, S., S. Mirabbasi, and A. Ivanov
Conference NameCircuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Pagination6138 - 6141 Vol. 6
Date Publishedmay.
Keywords0.18 micron, 1.8 V, 5 GHz, 70 mW, ADC, analogue-digital conversion, CMOS, CMOS integrated circuits, comparator offset effect minimization, comparators (circuits), ENOB, flash A/D converter, high-speed low power operation, low-power electronics, low-swing operation, nontime-interleaved flash ADC, offset averaging, static DNL errors, static INL errors
Abstract

A 4-bit 5 GS/s flash analog-to-digital converter (ADC) is designed and simulated in a 0.18 mu;m CMOS technology. Low-swing operation both in the analog and the digital circuitry results in high-speed low power operation. The ADC dissipates 70 mW power from a 1.8 V supply while operating at 5 GHz. Offset averaging is used to minimize the effect of comparator offsets. Simulation results show that offset voltages with 67 mV standard deviation (i.e., 1 LSB) can be tolerated. Static INL and DNL errors are 0.34 LSB and 0.24 LSB respectively, and the ENOB is 3.65 bits. The simulation results of this non-time-interleaved flash ADC demonstrates a significant improvement in terms of power and area compared to those of previously reported ADCs.

URLhttp://dx.doi.org/10.1109/ISCAS.2005.1466041
DOI10.1109/ISCAS.2005.1466041

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