Power-delay metrics revisited for 90 nm CMOS technology

TitlePower-delay metrics revisited for 90 nm CMOS technology
Publication TypeConference Paper
Year of Publication2005
AuthorsSengupta, D., and R. Saleh
Conference NameQuality of Electronic Design, 2005. ISQED 2005. 6th International Symposium on
Pagination291 - 296
Date Publishedmar.
Keywords90 nm, circuit optimisation, CMOS integrated circuits, CMOS technology, delays, design metrics, design optimization, energy-delay product, feasible operating region, goodness metric, integrated circuit design, leakage currents, leakage power, nanoelectronics, nanotechnology, power-delay product

Recently, designers have been using the energy-delay product as a metric of goodness for CMOS designs due to certain perceived shortcomings of the more traditional power-delay product. As the industry moves to 90 nm technology, with higher leakage currents, it is an appropriate time to revisit existing design metrics. We provide a more general view of power and delay metrics for design optimization and then illustrate how these metrics can be used. To do so, a re-evaluation of the metrics, based on past and future trends, is carried out and a set of new metrics is proposed. Interestingly, the dominance of leakage power at 90 nm technology and beyond tends to reduce the feasible operating region. We also establish a fundamental relationship between the optimal operating points and the generalized design metrics. Moreover, our initial findings indicate that some designs may need to leak more than expected to achieve certain design targets, running somewhat counter to conventional wisdom.


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