Memory switching effects in a-Si/c-Si heterojunction bipolar structures

TitleMemory switching effects in a-Si/c-Si heterojunction bipolar structures
Publication TypeJournal Article
Year of Publication1992
AuthorsSamuilov, V. A., E. A. Bondarionok, D. Shulman, and D. L. Pulfrey
JournalElectron Device Letters, IEEE
Pagination396 -398
Date Publishedaug.
Keywords200 ns, 40 ns, amorphous semiconductors, bipolar process, elemental semiconductors, fall time, heterojunction bipolar structures, heterojunction bipolar transistors, load resistance, memory switching effects, negative current pulses, OFF state, ON state, positive current pulses, reversible switching, rise time, semiconductor storage, semiconductor switches, Si, silicon, three-terminal memory cell, three-terminal structure, VLSI

The authors report a three-terminal undoped amorphous silicon (a-Si)/p-n crystalline silicon (c-Si) structure, which exhibits OFF and ON states. An OFF state is characterized by a current in the structure in the low nanoampere range due to the large resistance of the undoped a-Si layer, while in the ON state the structure exhibits a large conductance and its current is determined in practice by the load resistance. Reversible switching between the two states with a rise time of about 40 ns and a fall time of about 200 ns was achieved by applying appropriate positive or negative current pulses to the base of the c-Si p-n junction. The structure can be integrated into a standard bipolar process, and, being of a size suitable for VLSI applications, may be useful as a basic three-terminal memory cell


a place of mind, The University of British Columbia

Electrical and Computer Engineering
2332 Main Mall
Vancouver, BC Canada V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949

Emergency Procedures | Accessibility | Contact UBC | © Copyright 2021 The University of British Columbia