System-on-Chip: Reuse and Integration

TitleSystem-on-Chip: Reuse and Integration
Publication TypeJournal Article
Year of Publication2006
AuthorsSaleh, R., S. Wilton, S. Mirabbasi, A. Hu, M. Greenstreet, G. Lemieux, P. P. Pande, C. Grecu, and A. Ivanov
JournalProceedings of the IEEE
Volume94
Pagination1050 -1069
Date Publishedjun.
ISSN0018-9219
Keywordsad hoc bus, analog intellectual property, design for testability, design-for-test methodologies, formal verification, hard cores, high level synthesis, industrial property, integrated circuit design, integrated circuit testing, integrated circuits design, integration issues, intellectual property cores, layout level designs, network-on-chip architectures, register-transfer level designs, reusable components integration, reuse issues, soft cores, system-on-chip, system-on-chip design, verification issues
Abstract

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design. In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.

URLhttp://dx.doi.org/10.1109/JPROC.2006.873611
DOI10.1109/JPROC.2006.873611

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