Clock skew verification in the presence of IR-drop in the power distribution network

TitleClock skew verification in the presence of IR-drop in the power distribution network
Publication TypeJournal Article
Year of Publication2000
AuthorsSaleh, R., S. Z. Hussain, S. Rochel, and D. OVERHAUSER
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Date PublishedJUN
Type of ArticleArticle
Keywordscircuit simulation, CMOS integrated circuits, integrated circuit interconnections, matrix decomposition, power distribution, relaxation methods, very large scale integration

Clocks are perhaps the most important circuits in high-speed digital systems. The design of clock circuitry and the quality of clock signals directly impact the performance of a very large scale integrated chip. Clock skew verification requires high accuracy and is typically performed using circuit simulators. However, in high-performance deep-submicrometer digital circuits, clocks are running at higher frequencies and are driving more gates than ever, thus presenting a higher current load on the power distribution network with the potential for substantial power grid voltage (IR)-drop. This IR-drop affects the clock timing and must be taken into account in the verification process. Since IR-drop is a full-chip phenomenon, the use of standard circuit simulation on both the clock circuitry and the power-grid is not practical, In this paper, we present a new methodology for the verification of clock delay and skew. An iterative technique is presented for clock simulation in the presence of full-chip dynamic IR-drop. The effect of IR-drop on the timing of clock signals is quantified on a small example, and demonstrated on a large chip.

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