Asynchronous IC interconnect network design and implementation using a standard ASIC flow

TitleAsynchronous IC interconnect network design and implementation using a standard ASIC flow
Publication TypeConference Paper
Year of Publication2005
AuthorsQuinton, B. R., M. R. Greenstreet, and S. J. E. Wilton
Conference NameComputer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Pagination267 - 274
Date Publishedoct.
Keywordsapplication specific integrated circuits, ASIC flow, asynchronous circuits, asynchronous interconnect design, circuit CAD, IC design, IC interconnect network design, integrated circuit design, integrated circuit interconnections, skew clock tree, synchronous inter-block pipeline stages, synchronous interconnects

The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem. Creating a low skew clock tree for synchronous inter-block pipeline stages is a significant challenge. Asynchronous interconnect does not require a global clock, and therefore, it has a potential advantage in terms of design effort. This paper presents an asynchronous interconnect design that can be implemented using a standard ASIC flow. This design is considered in the context of a simple interconnect network. The results demonstrate that there is a region of the design space where the implementation provides an advantage over a synchronous interconnect. A detailed comparison of power, area and latency of the two strategies is also provided for a range of IC scenarios.


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