Performance evaluation and design trade-offs for network-on-chip interconnect architectures

TitlePerformance evaluation and design trade-offs for network-on-chip interconnect architectures
Publication TypeJournal Article
Year of Publication2005
AuthorsPande, P. P., C. Grecu, M. Jones, A. Ivanov, and R. Saleh
JournalComputers, IEEE Transactions on
Pagination1025 - 1040
Date Publishedaug.
Keywordscommunication-centric interconnect fabrics, computer architecture, integrated circuit interconnections, IP networks, multiprocessing systems, multiprocessor system-on-chip platform, network-on-chip interconnect architecture, performance evaluation, system-on-chip

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.


a place of mind, The University of British Columbia

Electrical and Computer Engineering
2332 Main Mall
Vancouver, BC Canada V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949

Emergency Procedures | Accessibility | Contact UBC | © Copyright 2021 The University of British Columbia