Design of a switch for network on chip applications

TitleDesign of a switch for network on chip applications
Publication TypeConference Paper
Year of Publication2003
AuthorsPande, P. P., C. Grecu, A. Ivanov, and R. Saleh
Conference NameCircuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
PaginationV-217 - V-220 vol.5
Date Publishedmay.
Keywords50 to 100 nm, butterfly fat tree architecture, data transfer, design methodology, hardware overhead, heterogeneous IP blocks, integrated circuit interconnections, integrated circuit layout, intellectual property blocks, interconnect architecture, IP block interconnection, latency, network on chip applications, network routing, SoC design, switch design, switch-based network-centric architecture, switching networks, system-on-chip, ultra deep submicron technologies, VLSI, wormhole routing

System on Chip (SoC) design in the forthcoming billion transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. Some of the main problems in the ultra deep sub micron technologies characterized by gate lengths in the range of 50-100 nm arise from non-scalable global wire delays, failure to achieve global synchronization, errors due to signal integrity issues, and difficulties associated with non-scalable bus-based functional interconnect. These problems are addressed in this paper by introducing a new design methodology. A switch-based network-centric architecture to interconnect IP blocks is proposed. We introduce a butterfly fat tree architecture as an overall interconnect template. In this new interconnect architecture, switches are used to transfer data between IP blocks. To reduce overall latency and hardware overhead, wormhole routing is adopted. The proposed switch architecture supports this routing method. Initial implementation of the switch reveals that the total switch area is expected to amount to less than 2% of a large SoC.


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