A novel FPGA architecture supporting wide shallow memories

TitleA novel FPGA architecture supporting wide shallow memories
Publication TypeConference Paper
Year of Publication2001
AuthorsOldridge, S. W., and S. J. E. Wilton
Conference NameCustom Integrated Circuits, 2001, IEEE Conference on.
Pagination75 -78
Keywords9.46 Mbit, configuration memory, field programmable gate arrays, FPGA architecture, logic block, on-chip user storage, random-access storage, unused switch blocks, wide shallow memories

This paper presents a novel architecture for on-chip user storage in a FPGA. Shallow wide memories are provided by allowing the user to write and read the configuration memory in unused switch blocks. Implementing this technique on a 100 times;100 logic block FPGA with 128 tracks per channel gives a total of 9.46 Megabits of memory which can be assessed using an arbitrary word width. The circuitry to provide access to the configuration bits in this way consists of 3.58 transistors per bit, and results in a routing speed degradation of 11.6% (typical critical path degradation of 5%)


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