Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS

TitleLayout of Decoupling Capacitors in IP Blocks for 90-nm CMOS
Publication TypeJournal Article
Year of Publication2008
AuthorsMeng, X., R. Saleh, and K. Arabi
JournalVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
Pagination1581 -1588
Date Publishednov.
Keywordsapplication specific integrated circuits, application-specific integrated circuit designs, CMOS, CMOS integrated circuits, decoupling capacitors, electrostatic discharge, high-frequency effects, industrial property, integrated circuit layout, intellectual property blocks, IP blocks, MOS capacitors, reliability, size 90 nm

On-chip decoupling capacitors (decaps) in the form of MOS transistors are widely used to reduce power supply noise. This paper provides guidelines for standard cell layouts of decaps for use within Intellectual Property (IP) blocks in application-specific integrated circuit (ASIC) designs. At 90-nm CMOS technology and below, a tradeoff exists between high-frequency effects and electrostatic discharge (ESD) reliability when designing the layout of such decaps. In this paper, the high-frequency effects are modeled using simple equations. A metric is developed to determine the optimal number of fingers based on the frequency response. Then, a cross-coupled design is described that has been recently introduced by cell library developers to handle ESD problems. Unfortunately, it suffers from poor response times due the large resistance inherent in its design. Improved cross-coupled designs are presented that properly balance issues of frequency response with ESD performance, while greatly reducing thin-oxide gate leakage.


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