GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering

TitleGlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
Publication TypeJournal Article
Year of Publication2008
AuthorsLamoureux, J., G. Lemieux, and S. Wilton
JournalVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
Pagination1521 -1534
Date Publishednov.
Keywordsdynamic power minimization, edge alignment, field programmable gate arrays, field-programmable gate arrays, glitch filtering, glitching, glitchless, low-power electronics, programmable delay elements, static timing analysis

This paper describes GlitchLess, a circuit-level technique for reducing power in field-programmable gate arrays (FPGAs) by eliminating unnecessary logic transitions called glitches. This is done by adding programmable delay elements to the logic blocks of the FPGA. After routing a circuit and performing static timing analysis, these delay elements are programmed to align the arrival times of the inputs of each lookup table (LUT), thereby preventing new glitches from being generated. Moreover, the delay elements also behave as filters that eliminate other glitches generated by upstream logic or off-chip circuitry. On average, the proposed implementation eliminates 87% of the glitching, which reduces overall FPGA power by 17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Furthermore, since it is applied after routing, the proposed technique requires little or no modifications to the routing architecture or computer-aided design (CAD) flow.


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