On the interaction between power-aware FPGA CAD Algorithms

TitleOn the interaction between power-aware FPGA CAD Algorithms
Publication TypeConference Paper
Year of Publication2003
AuthorsLamoureux, J., and S. J. E. Wilton
Conference NameComputer Aided Design, 2003. ICCAD-2003. International Conference on
Pagination701 - 708
Date Publishednov.
KeywordsCAD, clustering algorithm, computer aided design, delay models, delays, energy estimation, field programmable gate array, field programmable gate arrays, FPGA CAD tools, FPGA power consumption, low-power electronics, lower power FPGA circuitry design, network routing, placement algorithm, power aware FPGA CAD algorithms, power aware technology mapping, routing algorithms, software tools

As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be developed. Before designing low-power FPGA circuitry, architectures, or CAD tools, we must first determine where the biggest savings (in terms of energy dissipation) are to be made and whether these savings are cumulative. In this paper, we focus on FPGA CAD tools. Specifically, we describe a new power-aware CAD flow for FPGAs that was developed to answer the above questions. Estimating energy using very detailed post-route power and delay models, we determine the energy savings obtained by our power-aware technology mapping, clustering, placement, and routing algorithms and investigate how the savings behave when the algorithms are applied concurrently. The individual savings of the power-aware technology-mapping, clustering, placement, and routing algorithms were 7.6%, 12.6%, 3.0%, and 2.6% respectively. The majority of the overall savings were achieved during the technology mapping and clustering stages of the power-aware FPGA CAD flow. In addition, the savings were mostly cumulative when the individual power-aware CAD algorithms were applied concurrently with an overall energy reduction of 22.6%.


a place of mind, The University of British Columbia

Electrical and Computer Engineering
2332 Main Mall
Vancouver, BC Canada V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949

Emergency Procedures | Accessibility | Contact UBC | © Copyright 2021 The University of British Columbia