Programmable BIST space compactors

TitleProgrammable BIST space compactors
Publication TypeJournal Article
Year of Publication1996
AuthorsIvanov, A., B. K. Tsuji, and Y. Zorian
JournalComputers, IEEE Transactions on
Pagination1393 -1404
Date Publisheddec.
KeywordsBIST space compaction, built-in self test, built-in self-test, combinational PSCs, design for testability, genetic algorithms, integrated circuit testing, internal circuit nodes, logic testing, optimization search method, programmable space compactors, test data compaction

We address test data compaction for built-in self-test (BIST). The thrust of the work focuses on BIST space compaction, a process increasingly required when a large number of internal circuit nodes need to be monitored during test but where area limitations preclude the association of observation latches for all the monitored nodes. We introduce a general class of space compactors denoted as programmable space compactors (PSCs). Programmability enables highly-effective space compactors to be designed for circuits under test (CUT) subjected to a specific set or test patterns. Circuit-specific information such as the fault-free and expected faulty behavior of a circuit are used to choose PSCs that have better fault coverage and/or lower area costs than the commonly-used parity function. Finding optimal PSCs is a difficult task since the space of possible PSC functions is extremely large and grows exponentially with the number of lines (nodes) to be compacted. We describe an optimization search method based on genetic algorithms for finding combinational PSCs. The factors used to assess the effectiveness of a PSC are its fault coverage and implementation area


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