Analog IP design flow for SoC applications

TitleAnalog IP design flow for SoC applications
Publication TypeConference Paper
Year of Publication2003
AuthorsHamour, M., R. Saleh, S. Mirabbasi, and A. Ivanov
Conference NameCircuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
PaginationIV-676 - IV-679 vol.4
Date Publishedmay.
Keywordsanalog IP authoring flow, analog IP design flow, analog IP hardening, analog/mixed-signal portion, analogue processing circuits, circuit CAD, IC design process, integrated circuit design, phase locked loop, phase locked loops, reusable analog IP, SoC applications, system-on-chip, VCO, voltage-controlled oscillators

The analog/mixed-signal (AMS) portion of the IC design process continues to be a major bottleneck, slowing the progress towards fully integrated system-on-chip (SoC) designs. A clear definition of reusable analog IP and an analog IP authoring flow has not emerged as yet, although many efforts are underway in industry and academia to establish these notions. In this work, practical definitions of analog IP and an associated design process is proposed A methodology is developed for analog IP hardening. The VCO of a phase locked loop (PLL) is chosen to illustrate the process due to the increasing importance of PLLs in SoC designs.


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