Hazard-Aware Performance Prediction for Automatic Instruction-Set Selection

TitleHazard-Aware Performance Prediction for Automatic Instruction-Set Selection
Publication TypeConference Paper
Year of Publication2006
AuthorsHallschmid, P., and R. Saleh
Conference NameVLSI Design, Automation and Test, 2006 International Symposium on
Pagination1 -4
Date Publishedapr.
Keywordsapplication specific instruction set processors, application specific integrated circuits, automatic instruction set selection, hazard-aware predictor, high level description, high level synthesis, instruction enumeration algorithm, instruction selection algorithm, instruction sets, integrated circuit design, microprocessor chips, prediction error

Recent research in the area of application specific instruction set processors (ASIPs) has focused on the automatic selection of a custom instruction set based on a high level description of the application. Existing methods perform instruction selection under the assumption that data hazards can be ignored due to functional unit forwarding. This paper addresses data hazards in the ASIP flow when functional unit to functional unit forwarding is too expensive. This is accomplished by devising a "hazard-aware" predictor for measuring the impact of custom instructions on performance. Results show that our predictor reduces prediction error from 50% to 15% compared to the existing simple predictor and with a fraction of the run-time of rescheduling. When incorporated into an instruction enumeration and selection algorithm, our predictor reduces the total schedule length by as much as 8.4%


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