A flexible network-on-chip simulator for early design space exploration

TitleA flexible network-on-chip simulator for early design space exploration
Publication TypeConference Paper
Year of Publication2008
AuthorsGrecu, C., A. Ivanov, R. Saleh, C. Rusu, L. Anghel, P. P. Pande, and V. Nuca
Conference NameMicrosystems and Nanoelectronics Research Conference, 2008. MNRC 2008. 1st
Pagination33 -36
Date Publishedoct.
Keywordscircuit simulation, electronic engineering computing, flexible network-on-chip simulator, flit-level message-passing mechanism, input trace files, message passing, network-on-chip, network-on-chip communication architectures, on-chip communication fabrics, routing schemes, synthetic traffic generators, telecommunication network routing
Abstract

The communication requirements of large multi-core systems are convened by on-chip communication fabrics generally referred to as networks-on-chip (NoC). We have designed a simulation environment that allows early exploration of the performance and cost parameters of network-on-chip communication architectures, which is able to handle arbitrary topologies and routing schemes. The simulator implements a flit-level message-passing mechanism and supports application data specified as input trace files or generated at run-time by synthetic traffic generators.

URLhttp://dx.doi.org/10.1109/MNRC.2008.4683371
DOI10.1109/MNRC.2008.4683371

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