Methodologies and algorithms for testing switch-based NoC interconnects

TitleMethodologies and algorithms for testing switch-based NoC interconnects
Publication TypeConference Paper
Year of Publication2005
AuthorsGrecu, C., P. Pande, B. Wang, A. Ivanov, and R. Saleh
Conference NameDefect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on
Pagination238 - 246
Date Publishedoct.
Keywordsbuffer circuits, FIFO buffers, integrated circuit interconnections, integrated circuit testing, logic circuits, logic switching blocks, logic testing, network-on-chip, NoC interconnect testing, NoC topology, recursive testing, switched based NoC interconnects

In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with different degrees of parallelism in each case. Our test methodologies cover the logic switching blocks and the FIFO buffers that are the basic components of NoC fabrics. The paper concludes with test time evaluations for different NoC topologies and sizes.


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