An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic

TitleAn FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic
Publication TypeJournal Article
Year of Publication2008
AuthorsFoist, R. B., C. S. Grecu, A. Ivanov, and R. Turner
JournalEducation, IEEE Transactions on
Pagination312 -318
Date Publishedaug.
Keywordselectrical engineering students, electronic engineering education, embedded PowerPC subsystem core, embedded processor design, embedded systems, field programmable gate arrays, FPGA design project, further education, graduate students, hardware-software codesign, integrated circuit design, logic design, modules, processor block, supplementary laboratory module, system-on-chip, system-on-chip design, tutorial document, user logic, Xilinx field-programmable gate array

This paper presents a reference design and tutorial for an embedded PowerPC subsystem core with user logic in a Xilinx field-programmable gate array (FPGA). The design and tutorial were created to help graduate students who are doing research in complex electronic applications and want to prototype their designs in an FPGA. Specifically, the design provides a starting point for any application that requires an embedded processor plus user logic that is external to the processor block, but must interface to it. In addition, this material is useful as a supplementary laboratory module in advanced FPGA design (for senior- and graduate-level courses). The design project provides a practical introduction to system-on-chip (SOC) design, embedded processor design, hardware #x2013;software codesign, and general FPGA development. The authors' assessment shows that even third-year electrical engineering students can complete the tutorial successfully (within approximately three hours). The design database and tutorial document are publicly available and can be downloaded from a website at The University of British Columbia (UBC), Vancouver, BC, Canada.


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