A functional memory based architecture for running sorting

TitleA functional memory based architecture for running sorting
Publication TypeConference Paper
Year of Publication1999
AuthorsEldos, T., K. Mayyas, and T. Aboulnasr
Conference NameSignal Processing and Its Applications, 1999. ISSPA '99. Proceedings of the 5th International Symposium on
Pagination705 -708 vol.2
Keywordsarchitecture units, computational complexity, functional description, functional memory architecture, functional memory based architecture, hardware running sorter, memory architecture, real-time applications, running sorting algorithms, sorting

In real-time applications, software-level implementations of running sorting algorithms may not be able to meet the processing time requirements, particularly when the size of the running window is large. In this paper, we present a hardware running sorter based on a functional memory architecture. The proposed approach accelerates operations thus giving the new hardware the capability of completing the running sorting algorithm in log N+7 CPU cycles. Details of the architecture units are explained, and a functional description of its operation provided


a place of mind, The University of British Columbia

Electrical and Computer Engineering
2332 Main Mall
Vancouver, BC Canada V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949

Emergency Procedures | Accessibility | Contact UBC | © Copyright 2021 The University of British Columbia