Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays

TitlePower Implications of Implementing Logic Using FPGA Embedded Memory Arrays
Publication TypeConference Paper
Year of Publication2006
AuthorsChin, S. Y. L., C. S. P. Lee, and S. J. E. Wilton
Conference NameField Programmable Logic and Applications, 2006. FPL '06. International Conference on
Pagination1 -8
Date Publishedaug.
Keywords0.13 micron, Altera Stratix, architectural parameters, area efficient implementation, CMOS, CMOS logic circuits, digital storage, embedded memory arrays, EP1S40, field programmable arrays, field programmable gate arrays, FPGA, logic circuits, logic design, logic implementation, network routing, nonsquare memory, Poon power model, routed circuits, VPR

This paper investigates the power and energy implications of using embedded FPGA memory arrays to implement logic. Previous studies have shown that this technique provides extremely dense implementations of some types of logic circuits, however, these previous studies did not evaluate the impact on power. The authors measure the effects on power and energy as a function of three architectural parameters: the number of available memory arrays, the size of the memory arrays, and the flexibility of the memory arrays. It was shown in this paper that although embedded memories provide area efficient implementations of many circuits, this technique results in additional power consumption. When power can be traded off for density, it was also shown that for most array sizes, the arrays should be as flexible as possible, and that smaller memory arrays are more power efficient than large arrays. When larger arrays are desired for more density improvement, non-square memories with more rows than columns are better. The results were obtained from fully place and routed circuits using modified versions of VPR and the Poon power model. Several results were also verified through measurements on a 0.13mum CMOS FPGA (Altera Stratix EP1S40)


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