An improved "soft" eFPGA design and implementation strategy

TitleAn improved "soft" eFPGA design and implementation strategy
Publication TypeConference Paper
Year of Publication2005
AuthorsAken'Ova, V. C., G. Lemieux, and R. Saleh
Conference NameCustom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Pagination179 - 182
Date Publishedsep.
Keywordsapplication specific integrated circuits, architecture-specific tactical standard cells, ASIC flow, delay overhead, eFPGA design, field programmable gate arrays, FPGA CAD tools, GILES that, integrated circuit design, logic capacity, logic design, logic quality, programmable logic, programmable logic devices

A recently proposed "soft" eFPGA methodology was used to create small amounts of programmable logic using the ASIC flow, but it incurs significant overhead. In this paper, it is shown that architecture-specific tactical standard cells can reduce the area and delay overhead of the previous approach by 58% and 40% respectively. It is also shown that by imposing a structured design and layout approach, the logic capacity and quality of standard-cell-based eFPGAs can be significantly improved. Finally, it is shown that our improved ASIC flow approach can create layouts that are competitive with another approach called GILES that uses custom FPGA CAD tools and nonstandard cells for tile layout purposes.


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