Steve Wilton, Tony Ngai (Altera), Jonathan Rose, Zvonko Vranesic (University of Toronto)
With recent dramatic improvements in integrated circuit technology, more transistors than ever are available to IC designers. The impact of improving process technology is very evident in the evolution of field-programmable gate arrays (FPGAs) and FPGA-based reconfigurable systems (boards and multi-chip modules). In the past, such systems have been primarily used to implement small logic subcircuits, but as these devices grow, FPGAs and reconfigurable systems are being used to implement much larger circuits. An important difference between these larger circuits and the smaller subcircuits that have traditionally been implemented on reconfigurable devices is that the larger circuits often contain significant amounts of memory. This means that efficient architectural support for memory in next-generation FPGAs and FPGA-based systems is critical.
A key requirement of this memory support is the ability to accommodate various numbers, sizes, and shapes of memories. In this project, we developed an architecture for field-configurable memory that is flexible enough to implement the storage requirements of a wide variety of such circuits. The architecture was defined, and a proof-of-concept chip was implemented and tested.
Such an architecture can be used in two ways. First, it can be used a stand-alone device, in which the memory pins are connected directly to I/O pads. Such a chip would be valuable in reconfigurable systems consisting of FPGAs, memory devices, and interconnect. These systems have been used to achieve significant speedups in many compute-intensive applications (compared to software implementations), as well as being used as an efficient medium for logic emulation. In many of these systems, user memories are packed into standard off-the-shelf memory chips. These user memories typically have a different size or aspect ratio than the physical memory devices. When this happens, either memory is wasted, or the user memories must be time-multiplexed onto the memory chips. By providing memory resources that can better adapt to the requirements of circuits, more efficient circuit implementations are possible.
Our architecture can also be embedded into an FPGA to provide on-chip configurable memory. On-chip memory has a number of advantages over off-chip memory: it reduces the system cost by decreasing the number of chips required to fully implement a system, it often allows for faster clock rates since external pins (and board-level traces) need not be driven with each memory access, and it frees I/O pins that would otherwise be devoted to address and data connections. Although FPGAs with significant amounts of on-chip memory are available from several vendors, there has been little published work that compares and evaluates configurable memory architectures. The extension of the architecture to on-chip applications is being addressed in a separate project .