Programmable System-on-a-Chip:

Kim Bozman, Peter Hallschmid, Noha Kafafi, Tony Wong, James Wu, Andy Yan, Steve Wilton, Resve Saleh , University of British Columbia

Recent years have seen impressive improvements in the achievable density of integrated circuits. In order to maintain this rate of improvement, designers need new techniques to handle the increased complexity inherent in these large chips. One such emerging technique is the System-on-a-Chip (SoC) design methodology. In this methodology, pre-designed and pre-verified blocks, often called cores or intellectual property (IP), are obtained from internal sources or third-parties, and combined onto a single chip. These cores may include embedded processors, memory blocks, or circuits that handle specific processing functions. The SoC designer, who would have only limited knowledge of the structure of these cores, could then combine them onto a chip to implement complex functions.

No matter how seamless the SoC design flow is made, and no matter how careful an SoC designer is, there will always be some chips that are designed, manufactured, and then deemed unsuitable. This may be due to design errors not detected by simulation or it may be due to a change in requirements. This problem is not unique to chips designed using the SoC methodology. However, the SoC methodology provides an elegant solution to the problem: one or more programmable logic cores can be incorporated into the SoC. The programmable logic core is a flexible logic fabric that can be customized to implement any digital circuit after fabrication. Before fabrication, the designer embeds a programmable fabric (consisting of many uncommitted gates and programmable interconnects between the gates). After the fabrication, the designer can then program these gates and the connections between them.

In this project, we are studying the use of programmable logic within the SoC design paradigm. So far, we have focused primarily on architecture issues, and have concentrated on the differences between an embedded FPGA logic core and a standalone FPGA architecture.

A major contribution has been the development of a synthesizable programmable logic core. In this approach, vendors supply a synthesizable version of their programmable logic core (a soft core) and the integrated circuit designer synthesizes the programmable logic fabric using standard cells. Although this technique suffers increased speed, density, and power overhead, the task of integrating such cores is far easier than the task of integrating hard cores into an ASIC. For very small amounts of logic, this ease of use may be more important than the increased overhead. We have developed two synthesizable programmable logic core architectures, along with the associated place and route CAD tools.

Funding for this project has been obtained from Altera Corporation and through the Micronet NCE.

Publications from this research project:

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