Steve Wilton, Jonathan Rose (University of Toronto), Zvonko Vranesic (University of Toronto)
With the ever-improving technology available to integrated circuit designers, a problem central to all of computer-aided design research has come to light: in order to effectively evaluate candidate algorithms, appropriately-sized benchmark circuits are required, but these benchmark circuits are not available from users until the tools that support such large circuits are available. This is especially a problem in the design of algorithms that support Field-Programmable Gate Arrays (FPGAs) or in the design of next-generation FPGA architectures. Traditionally, FPGAs have been used to implement fairly small logic subcircuits, often the ``glue-logic'' portions of larger systems. As FPGAs get larger, however, they are beginning to be used to implement entire systems. These systems look significantly different than the smaller logic subcircuits. Nonetheless, much FPGA CAD tool and architecture research uses existing circuits, such as those available from Programmable Electronics Performance Corporation (PREP) or the Microelectronic Center of North Carolina (MCNC), as benchmarks. These circuits were originally intended for devices that are often an order-of-magnitude smaller than those being studied today, and thus may result in misleading conclusions, possibly leading to ineffective and/or inefficient CAD tools and devices.
One key difference between the larger systems that will be implemented in future FPGAs and the smaller logic subcircuits that have traditionally been implemented on FPGAs is that the larger systems often contain memory. FPGAs with on-chip memory are available from most FPGA vendors and are the subject of a related research project. In order to effectively compare configurable memory architectures and the related CAD tools, benchmark circuits containing both logic and memory are required. Currently, however, there is no such publicly available benchmark suite.
In this project, we are developing a tool, SCIRC, that stochastically generates realistic benchmark circuits containing both logic and memory. Since the circuits are generated stochastically, as many circuits as required can be created. In addition, the circuits are not limited to the size of available "real" benchmarks; the circuit size can be adjusted to meet the capacity of the device or CAD tool being evaluated.
When stochastically generating circuits, it is vital that the resulting circuits "look" as realistic as possible. In order to understand the nature of digital circuits with memory, we performed a detailed structural analysis of 171 real circuits, each with both memory and logic components. Although we did not have complete netlists for these circuits, we were able to gather statistics regarding the number, sizes, shapes, and other key characteristics of these memories. In addition, we were able to identify common patterns for the interconnect between memory and logic. These statistics and patterns were then incorporated into the circuit generator, ensuring the the generated circuits have many of the same properties as the original real circuits.