Imran Masud, Jason Clifford, Steve Wilton
An FPGA architecture consists of programmable logic elements and a programmable routing fabric. In commercial architectures, the routing consumes most of the chip area, and is responsible for most of the circuit delay. As FPGAs are migrated to more advanced technologies, the routing fabric becomes even more important. Thus, there has been a great deal of recent interest in developing efficient FPGA routing architectures.
There are two components to consider in FPGA routing: intra-cluster routing and inter-cluster routing. So far, we are focusing on the routing between clusters. One of the key components of this routing in a switch block. A switch block is a programmable interconnect block that is found at the intersection of each horizontal and vertical routing channel. A switch block programmably connects each incoming track to a number of outgoing tracks. Clearly, the flexibility of each switch block is key to the overall flexibility and routability of the device. Since the transistors in the switch block add capacitance loading to each track, the switch block has a significant effect on the speed of each routable connection, and hence the speed of the FPGA as a whole. In addition, since such a large portion of an FPGA is devoted to routing, the chip area required by each switch block will have a large effect on the achievable logic density of the device. Thus, the design of a good switch block is of the up-most importance.
As part of this project, we have developed a new switch block topology which outperforms all previous switch blocks over a wide range of segmented architectures in terms of area, with virtually no impact on speed. For segments of length four, our switch block results in an FPGA with 13 percent fewer transistors in the routing fabric.