J. Das, A. Lam, S. Wilton, P. Leong, W. Luk, "An Analytical Model Relating FPGA Architecture to Logic Density and Depth", to appear in IEEE Transactions on Very-Large Scale (VLSI) Integration.
[abstract][pdf]
J. Das, S.J.E. Wilton, "An Analytical Model Relating FPGA Architecture Parameters to Routability",
International Symposium on Field-Programmable Gate Arrays (FPGA), Feb 2011 (short paper), pp. 181-184.
[abstract][pdf][slides]
A. Lam, "An Analytical Model of FPGA Logic Resource Utilization for Architecture Development",
MASc Thesis, University of British Columbia, Feb 2010.
[abstract][pdf]
E. Hung, H. Yu, T. Chau, P.H.W. Leong, S.J.E. Wilton,
"A Detailed Delay Path Model for FPGAs",
International Conference on Field-Programmable Technology, Dec 2009, pp. 96-103.
A.M. Smith, G.A. Constantinides, S.J.E. Wilton, P.Y.K. Cheung,
"Concurrently Optimizing FPGA Architecture
Parameters and Transistor Sizing:
Implications for FPGA Design",
International Conference on Field-Programmable Technology, Dec 2009, pp. 54-61.
[abstract] [pdf]
J. Das, S.J.E. Wilton, W. Luk, P.H.W. Leong, "Modeling Post-Techmapping and Post-Clustering FPGA Circuit Depth", in International Conference on Field-Programmable Logic, August 2009, pp. 205-211.
[abstract] [pdf] [slides]
A.M. Smith, J. Das, S.J.E. Wilton,
"Wirelength Modeling for Homogeneous and Heterogeneous FPGA
Architectural Development",
ACM International Symposium on
Field-Programmable Gate Arrays, Monterey, CA, Feb 2009.
[abstract] [pdf]
A. Lam, S.J.E. Wilton, P. Leong, W. Luk,
"An Analytical Model Describing the Relationships between
Logic Architecture and FPGA Density",
International Conference on Field-Programmable Logic
and Applications, Sept. 2008.
[abstract] [pdf] [code]
FPGA CAD Scalability:
S.Y.L. Chin, S.J.E. Wilton, Towards Scalable FPGA CAD Through Architecture, ACM International Symposium on Field-Programmable Gate Arrays, February 2011, pp. 143-152.
[abstract][pdf]
C. Mark, S. Chin, L. Shannon, S.J.E. Wilton, " Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation", to appear in ACM Transactions on Embedded Computing Systems, accepted Jan 2010.
G. Smecher, S. Wilton, G. Lemieux, "Self-Hosted Placement for Massively Parallel Processor Arrays",
International Conference on Field-Programmable Technology, Dec 2009, pp. 159-166.
S. Chin, S.J.E. Wilton, "An Analytical Model Relating FPGA Architecture and Place and Route Runtime", in International Conference on Field-Programmable Logic, August 2009, pp. 146-153.
[abstract] [pdf]
S. Chin, S.J.E. Wilton. "Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms",
ACM Transactions on Reconfigurable Technology and Systems (TRETS),
vol. 1, no. 4, Jan. 2009, pp. 1-20.
[abstract] [pdf]
C. Mark, A. Shui, S.J.E. Wilton, "A System-Level Stochastic Circuit Generator for FPGA Architecture Evaluation",
in International Conference on Field-Programmable Technology,
Taipei, Taiwan, December 2008.
[abstract] [pdf] [code]
C. Mark, "A System-Level Synthetic Circuit Generator for
FPGA Architectural Analysis", MASc Thesis, University of British Columbia,
Nov. 2008
[abstract][pdf]
S. Chin, S.J.E. Wilton, "Memory Footprint Reduction For FPGA Routing Algorithms", in the International Conference on Field-Programmable Technology, Kokurakita, Japan, December 2007, pp. 1-8.
Best Paper Award [abstract] [pdf] [code]
Post-Silicon Debug:
E. Hung, S.J.E. Wilton, "On Evaluating Signal Selection Algorithms for Post-Silicon Debug",
International Symposium on Quality Electronic Design (ISQED), March 2011.
B.R. Quinton, A.M. Hughes, S.J.E. Wilton, "Post-Silicon Debug of Complex Multi Clock and Power Domain ICs",
IEEE International Workshop on Silicon Debug and Diagnosis, March 2010.
J. Kuan, S. Wilton, T. Aamodt, "Accelerating Trace Computation in Post-Silicon Debug",
to appear in International Symposium on Quality Electronic Design, San Jose, CA, March 2010. (poster)
M. Gort, "Practical Considerations for Post-Silicon Debug using BackSpace",
MASc Thesis, University of British Columbia, Aug 2009.
[abstract][pdf]
F.M. De Paula, M. Gort, A.J. Hu, S.J.E. Wilton,
"Backspace: Moving Towards Reality",
in Microprocessor Test and Verification Workshop,
Austin, TX, December 2008.
[abstract] [pdf]
F.M. De Paula, M. Gort, A.J. Hu, S.J.E. Wilton,
"Backspace: Formal Analysis for Post-Silicon Debug",
in
Formal Methods in Computer-Aided Design,
Portland, OR, November 2008.
[abstract] [pdf]
B.R. Quinton, "A Reconfigurable Post-Silicon Debug Infrastructure for Systems-on-Chip",
Ph.D. Thesis, University of British Columbia, 2008.
[abstract][pdf]
B.R. Quinton, S.J.E. Wilton, " Programmable Logic Core Enhancements for High Speed On-Chip Interfaces",
to appear in IEEE Transactions on VLSI.
B.R. Quinton, M.R. Greenstreet, S.J.E. Wilton, "Practical Asynchronous Interconnect Network Design", in IEEE Transactions on Very-Large Scale Integration (VLSI), vol. 16, no. 5, May 2008, pp 579-588.
S.J.E. Wilton, B. Quinton, C.H. Ho, P.H.W. Leong, W. Luk, "A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications", in ACM Transactions on Reconfigurable Technology and Systems, vol. 1, no. 1, March 2008, pp 7.1-7.25.
B. Quinton, S.J.E. Wilton,
"Embedded Programmable Logic Core Enhancements for System
Bus Interfaces",
in the International Conference on Field-Programmable Logic
and Applications, Amsterdam, August 2007, pp. 202-209.
[abstract] [pdf]
B.R. Quinton, S.J.E. Wilton,
"Programmable Logic Core Based Post-Silicon Debug For SoCs",
in the 4th IEEE Silicon Debug and
Diagnosis Workshop, Germany, May 2007.
[abstract] [pdf] [slides]
B.R. Quinton, S.J.E. Wilton,
"Post-Silicon Debug Using Programmable Logic Cores",
in the International Conference on Field-Programmable Technology,
Singapore, December 2005.
[abstract] [pdf]
B.R. Quinton, M. Greenstreet, S.J.E. Wilton,
"Asynchronous IC Interconnect Network Design and
Implementation Using a Standard ASIC Flow", in
the IEEE International Conference on Computer Design, October 2005, pp. 267-274.
[abstract] [pdf] [slides]
B.R. Quinton, S.J.E. Wilton, "Concentrator Access Networks for Programmable Logic Cores on SoCs" in the IEEE International Symposium on Circuits and Systems, May 2005, pp. 45-48.
[abstract] [pdf]
Power-Aware FPGAs and CAD
A.A.M. Bsoul, S.J.E. Wilton, "An FPGA Architecture Supporting Dynamically Controlled Power Gating", International Conference on Field-Programmable Technology (FPT'10), Beijing, China, Dec. 2010.
[abstract][pdf][slides]
P. Jamieson, W. Luk, S.J.E. Wilton, G. Constantinides,
"An Energy and Power Consumption Analysis of FPGA Routing Architectures",
to appear at International Conference on Field-Programmable Technology,
Dec. 2009 (poster presentation), pp. 324-327.
[abstract] [pdf] [code]
J. Lamoureux, S.J.E. Wilton, "On the Interaction between
Power and Flexibility of FPGA Clock Networks", to appear in
ACM Transactions on Reconfigurable Technology and Systems.
[abstract] [pdf]
C.H. Ho, P. Leong, W. Luk, S.J.E. Wilton,
"Rapid Estimation of Power Consumption for Hybrid FPGAs",
to appear at International Conference on Field-Programmable Logic
and Applications, Sept. 2008.
Distinguished Paper Award
J. Lamoureux, G.G. Lemieux, S.J.E. Wilton,
"GlitchLess: Dynamic Power Minimization in FPGAs through
Edge Alignmnet and Glitch Filtering",
to appear in IEEE Transactions on VLSI.
[abstract] [pdf]
S. Chin, C. Lee, S.J.E. Wilton,
"On the Power Dissipation of Embedded Memory Blocks
Used to Implement Logic in Field-Programmable Gate Arrays",
in International Journal of Reconfigurable Computing,
vol 2008, no. 1, 13 pages.
[abstract] [pdf]
J. Lamoureux, S.J.E. Wilton,
"Clock-Aware Placement for FPGAs",
in the International Conference on Field-Programmable Logic
and Applications, Amsterdam, August 2007,
pp. 124-131.
J. Lamoureux, G.G. Lemieux, S.J.E. Wilton,
"GlitchLess: An Active Glitch Minimization Technique for FPGAs",
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays,
Monterey, CA, February 2007.
[abstract] [pdf]
N. Chan King Choy, S.J.E. Wilton,
"Activity-Based Power Estimation and
Characterization of DSP and Multiplier Blocks
in FPGAs", International
Conference on Field-Programmable Technology
(poster presentation), Bangkok, Thailand,
December 2006.
S.Y.L. Chin, C.S.P. Lee, S.J.E. Wilton,
"Power Implications of Implementing Logic using FPGA Embedded Memory Arrays",
International Conference on Field-Programmable Logic
and Applications, Madrid, Spain, August 2006.
J. Lamoureux, S.J.E. Wilton,
"Activity Estimation for Field-Programmable Gate Arrays",
International Conference on Field-Programmable Logic
and Applications, Madrid, Spain, August 2006.
J. Lamoureux, S.J.E. Wilton, "FPGA Clock Network Architecture: Flexibility vs. Area and Power", ACM/SIGDA International Symposium on Field-Programmable Gate Arrays,
Monterey, California, Feb 2006.
[abstract] [pdf]
C.T. Chow, L.S.M. Tsui, P.H.W. Leong, W. Luk, S. Wilton,
"Dynamic Voltage Scaling for Commerical FPGAs",
in the International Conference on
Field-Programmable Technology, Singapore,
December 2005.
Best Paper Award
J. Lamoureux and S.J.E. Wilton, "On the Interaction Between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays", Journal of Low Power Electronics, Vol. 1, No. 2, August 2005, pp. 119-132.
K.K.W. Poon, S.J.E. Wilton, A. Yan, "A Detailed Power Model for Field-Programmable Gate Arrays",
in ACM Transactions on Design Automation of Electronic Systems (TODAES),
Vol. 10, Issue 2, April 2005, pp. 279-302.
[abstract] [pdf] [code].
S.J.E. Wilton, S-S. Ang, W. Luk, "The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays'',
in International Conference on
Field-Programmable Logic and its Applications, Antwerp, Belgium,
August 2004.
Included in Lecture
Notes in Computer Science 3203, Springer-Verlag, pp. 719-728.
Best Paper Award [abstract] [pdf] [slides]
J. Lamoureux, S.J.E. Wilton, ``On the Interaction between Power-Aware FPGA CAD Algorithms'',
in
IEEE International Conference on Computer-Aided Design
, November 2003.
[abstract] [pdf] [slides]
Julien Lamoureux, ``On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays'',
M.A.Sc. thesis, June 2003.
[abstract][pdf]
Kara K.W. Poon, ``Power Estimation for Field-Programmable
Gate Arrays'', M.A.Sc. thesis, August 2002.
[abstract][pdf]
K. Poon, S.J.E. Wilton, ``Sensitivity of FPGA Power Evaluation'',
in IEEE International Conference on Field-Programmable Technology,
December 2002, pp. 441-442.
[abstract] [pdf]
(unrefereed poster)
K. Poon, A. Yan, S.J.E. Wilton, ``A
Flexible Power Model for FPGAs'',
in the
12th International Conference on
Field-Programmable Logic and Applications, Sept 2002. Included in Lecture Notes in Computer Science 2438, Springer-Verlag, pp. 48-58.
[abstract] [pdf] [code].
Floating-Point FPGAs:
C.H. Ho, A.M. Smith, W. Luk, P.H.W. Leong, S.J.E. Wilton, "Optimizing
Floating Point Units in Hybrid FPGAs", to appear in
IEEE Transactions on Very-Large Scale (VLSI) Integration Systems.
C.H. Ho, C.W. Yu, P. Leong, W. Luk, S.J.E. Wilton, "Floating Point FPGA: Architecture and Modeling",
IEEE Transactions on Very-Large Scale (VLSI) Integration Systems,
vol. 17, no. 12, Dec 2009, pp. 1709-1718.
[abstract] [pdf]
C.W. Yu, W. Luk, S.J.E. Wilton, P.H.W. Leong, "Routing Optimization
for Hybrid FPGAs",
International Conference on Field-Programmable Technology, Dec 2009
(poster presentation), pp. 419-422.
C.W. Yu, J. Lamoureux, S. Wilton, P. Leong, W. Luk,
"The Coarse-Grained / Fine-Grained Logic Interface in FPGAs with Embedded Floating Point Units",
International Journal on Reconfigurable Computing, Volume 2008 (2008), Article ID 736203, 10 pages.
[abstract] [html]
C.W. Yu, A. Smith, P.H.W. Leong, W. Luk, S.J.E. Wilton,
"Optimizing Coarse-Grained Units in Floating Point Hybrid FPGA",
to appear in International Conference on Field-Programmable Technology,
Taipei, Taiwan, December 2008.
C.W. Yu, J. Lamoureux, S. Wilton, P.H.W. Leong, W. Luk,
"The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with
Embedded Floating-Point Arithmetic Units",
in Southern Programmable Logic Conference,
Bariloche, Argentina, March 2008, pp. 63-68.
Best Student Paper Award.
C.H.Ho, C.W.Yu, P.H.W. Leong, W. Luk, S.J.E. Wilton,
"Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications",
in the International Conference on Field-Programmable Logic
and Applications, Amsterdam, August 2007, pp. 196-201.
Distinguished Paper Award
C.H. Ho, P.H.W. Leong, W. Luk, S.J.E. Wilton, S. Lopez-Buedo,
"Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs",
in the IEEE International Symposium on Field-Programmable
Custom Computing Machines,
Napa, CA, Apr. 2006.
[abstract] [pdf]
Structured ASICs:
U. Ahmed, G. Lemieux, S. Wilton,
"Performance and Cost Trade-offs in
Metal-Programmable Structured ASICs (MPSAs)",
to appear in IEEE Transactions on Very-Large Scale (VLSI) Integration.
U. Ahmed, G. Lemieux, S. Wilton,
"The Impact of Interconnect Architecture on
Via-Programmed Structured ASICs (VPSAs)",
International Symposium on Field-Programmable Gate
Arrays (FPGA 2010), Feb. 2010, pp.
U. Ahmed, G. Lemieux, S. Wilton,
"Area, Delay, Power and Cost Trends for Metal-Programmable
Structured ASICs (MPSAs)",
International Conference on Field-Programmable Technology, Dec 2009
(poster presentation), pp. 278-284.
System-on-a-Chip Design:
S. Majzoub, R. Saleh, S. Wilton, R. Ward, "Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm", to appear in IEEE Transcations on Computer-Aided Design,
vol 29, no 5, pp. 816-829, May 2010.
S. Majzoub, R. Saleh, S. Wilton, R. Ward, "Simultaneous PVT-Tolerant Voltage-Island Formation and Core Placement for Thousand-Core Platforms", to appear in International Symposium on System-on-Chip, October 2009 (poster presentation)
[abstract] [pdf]
X. Meng, R. Saleh, S. Wilton, "Charge-Borrowing Decap: A Novel Circuit for Removal of Local Supply Noise Violations", to appear in IEEE Custom Integrated Circuits Conference, September 2009.
[abstract] [pdf]
S. Majzoub, R. Saleh, S. Wilton, R. Ward, "Removal-Cost Method: An Efficient Voltage Selection Algorithm for Multi-Core Platforms under PVT", to appear IEEE International SoC Conference, August 2009.
[abstract] [pdf]
S.J.E. Wilton, C.H. Ho, P.H.W. Leong, W. Luk, B. Quinton,
"A Synthesizable Datapath-Oriented Embedded FPGA Fabric",
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays,
Monterey, CA, February 2007.
[abstract] [pdf] [slides]
R. Saleh, S. Wilton, S. Mirabbasi, A. Hu, M. Greenstreet,
G. Lemieux, P. Pande, C. Grecu, A. Ivanov, "System-on-Chip: Reuse and Integration",
Proceedings of the IEEE, Vol. 94, No. 6, June 2006, pp. 1050-1069.
[abstract][pdf]
A. Yan, S.J.E. Wilton, "Product-Term Based Synthesizable Embedded Programmable Logic Cores",
IEEE Transactions on VLSI, Vol. 14, No. 5, May 2006, pp. 474-488.
[abstract][pdf]
S.J.E. Wilton, K. Bozman, N. Kafafi, J. Wu, "Method for constructing an integrated circuit device having fixed and
programmable logic portions and programmable logic architecture for use
therewith", U.S. Patent #6,983,442, Issued Jan 3, 2006.
P. Hallschmid, S.J.E. Wilton, " Routing Architecture Optimizations for High-Density Embedded Programmable IP Cores", IEEE Transactions on Very-Large Scale Integration (VLSI) Systems, Vol. 13, Issue 11, November 2005, pp. 1320-1324.
S.J.E. Wilton, N. Kafafi, J. Wu, K. Bozman, V. Aken'Ova, R. Saleh, "Design Considerations for Soft Embedded Programmable Logic Cores", IEEE Journal of Solid-State Circuits, vol. 40, no. 2, Feb 2005, pp. 485-497.
[abstract][pdf]
A. Yan, "Product-Term Based Synthesizable Embedded Programmable Logic Cores",
M.A.Sc. thesis, January 2005.
[abstract] [pdf] [slides]
T. Wong, S.J.E. Wilton, "Placement and Routing for Non-Rectangular Embedded Programmable Logic Cores in SoC Design", in the International Conference on Field-Programmable Technology, Brisbane, Australia, December 2004, pp. 65-72.
[abstract] [pdf]
J.C.H. Wu, "Implementation Considerations for "Soft" Embedded Programmable Logic Cores", M.A.Sc. thesis, October 2004.
[abstract] [pdf]
A. Yan, S.J.E. Wilton, ''Sequential Synthesizable
Embedded Programmable Logic Cores for System-on-Chip'',
in the IEEE Custom Integrated Circuits Conference ,
Orlando, FL, October 2004.
[abstract] [pdf]
A. Coppola, J. Stanley, S.J.E. Wilton, "Interface scheme for connecting a fixed circuitry block to a programmable logic core", U.S. Patent 6,747,479, Issued June 8, 2004.
A. Yan, S.J.E. Wilton, ``Product Term Embedded Synthesizable Logic Cores'',
in the IEEE International Conference on Field-Programmable Technology,
Tokyo, Japan, Dec. 2003, pp. 162-169. Best Paper Award [abstract] [pdf] [slides]
A. Coppola, J. Stanley, S.J.E. Wilton, "Interface scheme for connecting a fixed circuitry block to a programmable logic core", U.S. Patent 6,646,466, Issued Nov 11, 2003.
J.C.H. Wu, V. Aken'Ova, S.J.E. Wilton, R. Saleh, ``SoC Implementation
Issues for Synthesizable Embedded Programmable Logic Cores'',
in the IEEE Custom Integrated Circuits Conference,
San Jose, CA, Sept. 2003, pp. 45-48.
[abstract] [pdf]
N. Kafafi, K. Bozman, S.J.E. Wilton, ``Architectures and
Algorithms for Synthesizable Embedded Programmable Logic Cores'',
in the ACM International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, Feb 2003, pp. 1-9.
[abstract] [pdf] [slides]
S.J.E. Wilton, R. Saleh, ``Progammable Logic IP Cores
in SoC Design: Opportunities and Challenges'', in the
IEEE Custom Integrated Circuits Conference,
San Diego, CA, May 2001, pp. 63-66.
[abstract] [pdf]
T. Wong, ``Non-Rectangular Embedded Programmable Logic Cores'',
M.A.Sc. Thesis, May 2002.
[abstract][pdf]
P. Hallschmid, S.J.E. Wilton, ``Detailed Routing Architectures for
Embedded Programmable Logic IP Cores'',
in the
ACM/SIGDA International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, Feb. 2001, pp. 69-74.
[abstract] [pdf]
Heterogeneous Technology Mapping:
S.J.E. Wilton, ``Implementing Logic in FPGA Memory
Arrays: Heterogeneous Memory Architectures'',
in the IEEE International Conference on
Field-Programmable Technology, December 2002, pp. 142-149.
[abstract] [pdf] [slides]
E. Lin, S.J.E. Wilton, ``The Architecture of Dual-Mode FPGA
Embedded System Blocks'',
in IEEE Custom Integrated Circuits Conference,
May 2002, pp. 63-66.
[abstract] [pdf]
E. Lin, ``Product Term Mode Embedded Memory Arrays: Architectures and Algorithms'',
M.A.Sc. Thesis, September 2001.
[abstract][pdf]
E. Lin, S.J.E. Wilton, ``Macrocell Architectures for
Product Term Embedded Memory Arrays'',
in 11th International Conference on
Field-Programmable Logic and Applications, Aug 2001.
Best Paper Award [abstract] [pdf]
S.J.E. Wilton, ``Heterogeneous Technology Mapping
for Area Reduction in FPGAs with Embedded Memory Arrays'',
IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, Vol. 19, No. 1, Jan. 2000, pp. 56-68.
[abstract] [pdf]
S.J.E. Wilton, ``Heterogeneous Technology Mapping for FPGAs with
Dual-Port Embedded Memory Arrays'',
in the Eighth ACM/SIGDA International Symposium on
Field-Programmable Gate Arrays , Feb 2000, pp. 67-74.
[abstract] [pdf]
S.J.E. Wilton, `` Implementing Logic in FPGA Embedded Memory Arrays:
Architectural Implications'', in the IEEE Custom Integrated
Circuits Conference , May 1998.
[abstract] [pdf]
S.J.E. Wilton, ``SMAP: Heterogeneous Technology Mapping
for Area Reduction in FPGAs with Embedded Memory Arrays'',
in the ACM/SIGDA International Symposium on
Field-Programmable Gate Arrays , Feb. 1998.
[abstract] [pdf]
Reconfigurable Computing
Z. Kwok and S.J.E. Wilton,
"Register File Architecture Optimization in a Coarse-Grained
Reconfigurable Architecture", IEEE Symposium on Field-Programmable Custom Computing Machines,
April 2005.
[abstract] [pdf]
T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk
and P.Y.K. Cheung, "Reconfigurable Computing: Architectures and Design
Methods", IEE Proceedings: Computer & Digital
Techniques, Vol. 152, No. 2, March 2005, pp. 193-208.
[abstract] [pdf].
Included in B.M. Al-Hashimi (Ed.), "System on Chip: Next Generation Electronics",
IET, ISBN 0-86341-552-0/4, 2006. [details]
S.J.E. Wilton, N. Kafafi, B. Mei, S. Vernalde, "Interconnect Architectures for Modulo-Scheduled Coarse-Grained Reconfigurable Arrays", in the International Conference on Field-Programmable Technology, Brisbane, Australia, December 2004, pp. 33-40.
[abstract] [pdf]
Crosstalk-Aware Routing for FPGAs:
S.J.E. Wilton, ``A Crosstalk-Aware Timing-Driven Router for
FPGAs'', in the
ACM/SIGDA International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, Feb. 2001, pp. 21-28.
[abstract] [pdf]
Embedded Memory in an FPGA:
S.W. Oldridge and S.J.E. Wilton, "A Novel FPGA Architecture Supporting
Wide, Shallow Memories", in IEEE Transactions on Very-Large Scale Integration
(VLSI) Systems, Vol. 13, Issue 6, June 2005, pp. 758-762.
S.J.E. Wilton, C.W. Jones, J. Lamoureux, "An Embedded Flexible
Content-Addressable Memory Core for Inclusion in a Field-Programmable
Gate Array", in the IEEE International Symposium on
Circuits and Systems, Vancouver, B.C., May 2004, Vol. II, pp. 885-888.
[abstract] [pdf]
(refereed poster)
S.W. Oldridge, S.J.E. Wilton, "Placement
and Routing for FPGA Architectures Containing Wide Shallow
Memories", in the IEEE International Conference
on Field-Programmable Technology, Tokyo, Japan, December 2003, pp. 154-161.
C.W. Jones, S.J.E. Wilton, "Content-addressable Memory with
Cascaded Match, Read and Write Logic in a Programmable
Logic Device", U.S. Patent 6,622,204. Issued Sept. 16, 2003.
S.W. Oldridge, S.J.E. Wilton, ``A Novel FPGA Architecture Supporting Wide Shallow Memories'',
in the
IEEE Custom Integrated Circuits Conference,
San Diego, CA, May 2001, pp. 75-78.
[abstract] [pdf]
S.J.E. Wilton, J. Rose, Z.G. Vranesic, ``Structural Analysis and
Generation of Digital Circuits with Memory'',
IEEE Transactions on Very-Large Scale Integration Systems ,
vol. 9, no. 1, February 2001, pp.223-226.
[abstract]
[pdf]
Jason P. Clifford, Steven J.E. Wilton, ``Architecture of
Cluster-Based FPGAs with Memory'', in
IEEE Custom Integrated Circuits Conference, May 2000.
[abstract] [pdf]
William K.C. Ho, Steven J.E. Wilton, ``Logical-to-Physical Memory
Mapping for FPGAs with Dual-Port Embedded Arrays'',
in International Workshop on Field Programmable
Logic and Applications , Aug. 1999.
[abstract] [pdf]
S.J.E. Wilton, ``FPGA Embedded Memory Architectures: Recent
Research Results'',
in IEEE Pacific Rim Conference on Communications,
Computers and Signal Processing , Aug. 1999.
[abstract] [pdf]
S.J.E. Wilton, J. Rose, Z.G. Vranesic, ``The Memory/Logic Interface in FPGA's
with Large Embedded Memory Arrays'',
IEEE Transactions on Very-Large Scale Integration Systems ,
vol. 7, no. 1, March 1999.
[abstract]
S.J.E. Wilton, J. Rose, Z.G. Vranesic ``Memory-to-Memory
Connection Structures in FPGAs with Embedded Memory Arrays'',
ACM/SIGDA International Symposium on
Field-Programmable Gate Arrays , pp. 10-16, Feb. 1997.
[abstract] [postscript]
S.J.E. Wilton, J. Rose, Z.G. Vranesic ``Memory/Logic Interconnect Flexibility in FPGAs with Large Embedded Memory Arrays,''
IEEE Custom Integrated Circuits
Conference , May 1996.
[abstract] [pdf][html]
Steven J.E. Wilton, ``Architecture and Algorithms for Field-Programmable Gate Arrays with Embedded Memory,''
PhD thesis, University of Toronto, 1997.
[abstract][pdf]
Stand-alone Configurable Memories (can also be embedded in an FPGA):
S.J.E. Wilton, J.Rose, and Z.G. Vranesic, ``Architecture of centralized
field-configurable memory,'' in ACM/SIGDA International Symposium on
Field-Programmable Gate Arrays , pp. 97-103, 1995.
[abstract]
[pdf][html]
T.Ngai, J.Rose, and S.J.E. Wilton, ``An SRAM-Programmable
Field-Configurable Memory,'' IEEE Custom Integrated Circuits
Conference , pp. 499-502, 1995.
[abstract]
[pdf]
Detailed FPGA Routing Architectures
C.W. Jones, S.J.E. Wilton, ``Cascadable bus based crossbar switching in a Programmable Logic Device'',
U.S. Patent 6,710,623. Issued Mar 23, 2004.
C.W. Jones, S.J.E. Wilton, ``Cascadable bus based crossbar switch in a Programmable Logic Device'',
U.S. Patent 6,590,417. Issued July 8, 2003.
M. Imran Masud, ``FPGA Routing Structures: A Novel Switch Block and
Depopulated Interconnect Matrix Architecture'',
M.A.Sc. Thesis, December 1999.
[abstract][pdf]
M. Imran Masud, Steven J.E. Wilton, ``A New Switch Block
for Segmented FPGAs'',
in International Workshop on Field Programmable
Logic and Applications , Aug. 1999.
[abstract] [pdf]
Computer Architecture and Cache Access Time Modeling:
S.J.E. Wilton and N.P. Jouppi, ``CACTI: An enhanced cache access and cycle
time model,'' IEEE Journal of Solid-State Circuits , Vol. 31, No. 5, May 1996, pp 677-688.
[abstract][pdf][html]
N.P. Jouppi and S.J.E. Wilton, ``Tradeoffs in Two-Level On-Chip Caching,''
in 21st Annual International Symposium on Computer Architecture , 1994.
[also available as DEC WRL technical report number 93/3].
[abstract][postscript]
S.J.E. Wilton and Norman P. Jouppi, ``An Enhanced Access and Cycle Time
Model for On-Chip Caches,'' DEC WRL technical report number 93/5 , 1994
[abstract][postscript]
Multiprocessors:
S.J.E. Wilton and Z.G. Vranesic, ``Architectural Support for Block
Transfers in a Shared Memory Multiprocessor,'' in Fifth IEEE Symposium
on Parallel and Distributed Processing , pp. 51--54, Dec. 1993.
[abstract][pdf][html]
Steven J.E. Wilton, ``Block Transfers in a Shared-Memory Multiprocessor,''
Master's thesis, University of Toronto, 1992.
[abstract]
Miscellaneous:
D. Chiu, G. Lemieux, S. Wilton,
"Congestion-Driven Regional Re-clustering for Low Cost FPGAs",
International Conference on Field-Programmable Technology, Dec 2009, pp. 167-174.
S.J.E. Wilton, N. Chan King Choy, S.Y.L. Chin, K.K.W. Poon, "Field-Programmable Gate Array
Architectures", in Handbook of Algorithms for Physical Automation, eds. Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar, Nov 2008, pp 941-956
link
T. Rissa, S.J.E. Wilton, "Editorial: Special Issue on the 2005 International Conference on Field-Programmable Logic and Applications", IEE Proceedings: Computers and Digital Techniques, June 2006.
E. Charbon, F. Svelto, S.J.E. Wilton, ``Editorial'' (Introduction to the Special Issue on the 2002 Custom Integrated Circuits Conference),
IEEE Journal of Solid-State Circuits , Vol. 38, No. 3, March 2003.
T.T. Rueger, S.J.E. Wilton, ``Editorial'' (Introduction to the Special Issue on the 2001 Custom Integrated Circuits Conference),
IEEE Journal of Solid-State Circuits , Vol. 37, No. 3, March 2002, pp 267-269.
A. Yan, R. Cheng, S.J.E. Wilton, ``On the Sensitivity of
FPGA Architectural Conclusions to the Experimental Assumptions,
Tools, and Techniques'',
in the
ACM/SIGDA International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, Feb. 2002, pp. 147-156.
[abstract] [pdf]
W.W. Cheng, S.J.E. Wilton, B. Hamidzadeh, ``FPGA Implementation of a
Prototype WDM On-Line Scheduler'',
in the 10th International Conference on Field Programmable
Logic and Applications, August 2000.
[abstract] [pdf]
(refereed poster)
P.D. Kundarewich, S.J.E. Wilton, A.J Hu, ``A CPLD-based RC4 Cracking System'', in 1999 Canadian Conference on Electrical and Computer Engineering , May 1999.
[abstract] [pdf]
E. Casas, E. Lin, S. Wilton, ``An Inexpensive Laboratory for Teaching
Digital Logic and Microcomputer Design'', presented at the 1999
Canadian Conference on Computer Engineering Education , June 1999.
(unrefereed)
G. Feygin, P. Chow, P.G. Gulak, J.Chappel, G. Goodes, O. Hall, A. Sayes,
S. Singh, M.B. Smith, and S. Wilton, ``A VLSI Implementation of a Cascade
Viterbi Decoder with Traceback,'' in 1993 IEEE International Symposium
on Circuits and Systems , pp. 1945--1948, May 1993
[abstract] [pdf]