Floating Point FPGA: Architecture and Modeling
C.H. Ho, C.W. Yu, P. Leong, W. Luk, S.J.E. Wilton
IEEE Transactions on Very-Large Scale Integration Systems, Vol. 17, No. 12, Dec 2009, pp. 1709-1718.
Abstract
This paper presents an architecture for a reconfigurable
device that is specifically optimized for floating-point
applications. Fine-grained units are used for implementing control
logic and bit-oriented operations, while parameterized and
reconfigurable word-based coarse-grained units incorporating
word-oriented lookup tables and floating-point operations are
used to implement datapaths. In order to facilitate comparison
with existing FPGA devices, the virtual embedded block scheme
is proposed to model embedded blocks using existing field-programmable
gate array (FPGA) tools. This methodology involves
adopting existing FPGA resources to model the size, position, and
delay of the embedded elements. The standard design flow offered
by FPGA and computer-aided design vendors is then applied and
static timing analysis can be used to estimate the performance of
the FPGA with the embedded blocks. On selected floating-point
benchmark circuits, our results indicate that the proposed architecture
can achieve four times improvement in speed and 25 times
reduction in area compared with a traditional FPGA device.
(PDF Version)
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