A Detailed Power Model for Field-Programmable Gate Arrays

Kara K.W. Poon, Steven J.E. Wilton, Andy Yan

ACM Transactions on Design Automation of Electronic Systems

Abstract

Power has become a critical issue for FPGA vendors. Understanding the power dissipation within FPGAs is the first step to develop power-efficient architectures and CAD tools for FPGAs. This paper describes a detailed and flexible power model which has been integrated in the widely-used Versatile Place and Route (VPR) CAD tool. This power model estimates the dynamic, short-circuit, and leakage power consumed by FPGAs. It is the first flexible power model developed to evaluate architectural tradeoffs and the efficiency of power-aware CAD tools for a variety of FPGA architectures, and is freely available for non-commercial use. The model is flexible, in that it can estimate the power for a wide variety of FPGA architectures, and it is fast, in that it does not require extensive simulation, meaning it can be used to explore a large architectural space. We show how the model can be used to investigate the impact of various architectural parameters on the energy consumed by the FPGA, focusing on the segment leng

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