Activity-based Power Estimation and Characterization of DSP and Multiplier Blocks in FPGAs

Nathalie Chan King Choy

Master of Applied Science Dissertation, University of British Columbia, 2006

Abstract

Battery-powered applications and the scaling of process technologies and clock frequencies have made power dissipation a first class concern among FPGA vendors. One approach to reduce power dissipation in FPGAs is to embed coarse-grained fixed-function blocks that implement certain types of functions very efficiently. Commercial FPGAs contain embedded multipliers and “Digital Signal Processing (DSP) blocks” to improve the per- formance and area efficiency of arithmetic-intensive applications. In order to evaluate the power saved by using these blocks, a power model and tool flow are required.

This thesis describes our development and evaluation of methods to estimate the ac- tivity and the power dissipation of FPGA circuits containing embedded multiplier and DSP blocks. Our goal was to find a suitable balance between estimation time, modeling effort, and accuracy. We incorporated our findings to create a power model and CAD tool flow for these circuits. Our tool flow builds upon the Poon power model, and the Versa- tile Place and Route (VPR) CAD tool, which are both standard academic experimental infrastructure.

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