An Analytical Model of Logic Resource Utilization for FPGA Architecture Development
Andrew Lam
Master of Applied Science Dissertation, University of British Columbia, 2010
Abstract
Designers constantly strive to improve Field-Programmable Gate Array (FPGA)
performance through innovative architecture design. To evaluate
performance, an understanding of the effects of modifying logic blocks
structures and routing fabrics on performance is needed. Current
architectures are evaluated via computer-aided design (CAD)
simulations that are labourious and computationally-expensive
experiments to perform. A more scientific method, based on
understanding the relationships between architectural parameters
and performance will enable the rapid evaluation of new architectures,
even before the development of a CAD tool.
This thesis presents an analytical model that describes such
relationships and is based principally on Rent's Rule.
Specifically, it relates logic architectural parameters
to the area efficiency of an FPGA. Comparison to experimental
results show that our model is accurate. This accuracy combined
with the simple form of the model's equations make it a powerful
tool for FPGA architects to better understand and guide the development
of future FPGA architectures.
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