On the Tradeoff between Power and Flexibility of
FPGA Clock Networks
Julien Lamoureux, Steven J.E. Wilton
Abstract
FPGA clock networks consume a significant amount of power since they toggle every clock cycle and must be
flexible enough to implement the clocks for a wide range of different applications. The efficiency of FPGA
clock networks can be improved by reducing this flexibility; however, reducing the flexibility introduces stricter
constraints during the clustering and placement stages of the FPGA CAD flow. These constraints can reduce
the overall efficiency of the final implementation. This paper examines the tradeoff between the power
consumption and flexibility of FPGA clock networks.
Specifically, this paper makes three contributions. First, it presents a new parameterized clock network
framework for describing and comparing FPGA clock networks. Second, it describes new clock-aware
placement techniques that are needed to find a legal placement that satisfies the constraints imposed by the
clock network. Finally, it performs an empirical study to examine the tradeoff between the power consumption
of the clock network and the impact of the CAD constraints for a number of different clock networks with
varying amounts of flexibility.
The results show that the techniques used to produce a legal placement can have a significant influence on
power and the ability of the placer to find a legal solution. On average, circuits placed using the most effective
techniques dissipate 5% less overall energy and were significantly more likely to be legal than circuits placed
using other techniques. Moreover, the results show that the architecture of the clock network is also important.
On average, FPGAs with an efficient clock network were up to 14.6% more energy efficient compared to other
FPGAs.
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