CACTI: An Enhanced Cache Access and Cycle Time Model
Steven J.E. Wilton, Norman P. Jouppi
IEEE Journal of Solid-State Circuits, Vol 31, No. 5, May 1996, pages 677-688
Abstract
This paper describes an analytical model for the access and cycle times of
on-chip direct-mapped and set-associative caches. The inputs to the model are!
cache size, block size, and associativity, as well as array organization and
process parameters. The model gives estimates that are within 6%
of Hspice results for the circuits we have chosen.
This model extends previous models and fixes many of their major
shortcomings.
New features include models for the tag array, comparator,
and multiplexor drivers, non-step stage input slopes, rectangular
stacking of memory subarrays, a transistor-level decoder model,
column-multiplexed bitlines controlled by an additional array
organizational parameter, load-dependent size transistors for wordline
drivers, and output of cycle times as well as access times.
Software implementing the model is available via ftp.
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