On the Interaction Between Power-Aware FPGA CAD Algorithms
Julien Lamoureux, Steven J.E. Wilton
IEEE International Conference on Computer-Aided Design, Nov 2003
Abstract
As Field Programmable Gate Array (FPGA) power consumption continues to
increase, lower power FPGA circuitry, architectures, and Computer-Aided
Design (CAD) tools need to be developed. Before designing low-power FPGA
circuitry, architectures, or CAD tools, we must first determine where the
biggest savings (in terms of energy dissipation) are to be made and whether
these savings are cumulative. In this paper, we focus on FPGA CAD tools.
Specifically, we describe a new power-aware CAD flow for FPGAs that was
developed to answer the above questions.
Estimating energy using very detailed post-route power and delay models, we
determine the energy savings obtained by our power-aware technology mapping,
clustering, placement, and routing algorithms and investigate how the
savings behave when the algorithms are applied concurrently. The individual
savings of the power-aware technology-mapping, clustering, placement, and
routing algorithms were 7.6%, 12.6%, 3.0%, and 2.6% respectively. The
majority of the overall savings were achieved during the technology mapping
and clustering stages of the power-aware FPGA CAD flow. In addition, the
savings were mostly cumulative when the individual power-aware CAD
algorithms were applied concurrently with an overall energy reduction of
22.6%.
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