A System-Level Stochastic Circuit Generator for FPGA
Architecture Evaluation
Cindy Mark, Ava Shui, Steven J.E. Wilton
International Conference on Field-Programmable Technology, 2008
Abstract
We describe a stochastic circuit generator that can
be used to automatically create benchmark circuits for use in
FPGA architecture studies. The circuits consist of a hierarchy
of interconnected modules, reflecting the structure of circuits
designed using a system-on-chip design flow. Within each level of
hierarchy, modules can be connected in a bus, star, or dataflow
configuration. Our circuit generator is calibrated based on a
careful study of existing SoC circuits. We compare our circuits to
those generated by previous circuit generators, and characterize
our circuits with respect to the type of network used to connect
modules.
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