Modeling the Relationship between FPGA Architecture and Place and Route Runtime
Scott Y.L. Chin, Steven J.E. Wilton
International Conference on Field-Programmable Logic and Applications (FPL 2009)
Abstract
This paper presents an analytical model that relates the architectural
parameters of an FPGA to the place-and-route
runtimes of the FPGA CAD tools. We consider both a simulated
annealing based placement algorithm employing a
bounding-box wirelength cost function, and a negotiationbased
A* router. We also show an example application of
the model in early architecture evaluation.
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