Embedded Programmable Logic Core Enhancements for System Bus
Interfaces
Bradley R. Quinton and Steven J.E. Wilton
International Conference on Field-Programmable Logic and Applications (FPL 2007)
Abstract
Programmable logic cores (PLCs) offer a means of
providing post-fabrication re-configurability to a SoC
design. Circuits implemented in a PLC will inevitably
have lower timing performance and logic density than
fixed function circuits. This fundamental mismatch
makes the design of the interface between the PLC and
the rest of the SoC a challenging problem. In this paper
we focus on interfaces between circuits implemented in
PLCs and SoC system busses. We demonstrate
problems with existing implementation options and then
propose modifications to parts of the PLC architecture
to enable more efficient system bus interfaces. Our
results show that, on average, this modified architecture
improves interface timing by 36.4%, reduces CLB usage
by 7.9% and improves routability by 28.8% for circuits
that require system bus interfaces. We show that the
area overhead is less than 0.5% for circuits that do not
require bus interfaces.
Back to Steve Wilton's home page