The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays

Steven J.E. Wilton, Su-Shin Ang, Wayne Luk

International Conference on Field Programmable Logic and its Applications (FPL), 2004

Abstract

This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13um CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18um CMOS low-cost FPGA (Xilinx XC2S200). The results are obtained by both measurements and execution of vendor-supplied tools for power estimation. It is found that pipelining can reduce the amount of energy per operation by between 40% and 90%. Further reduction in energy consumption can be achieved by power-aware clustering, although the effect becomes less pronounced for circuits with a large number of pipeline stages.

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