SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays
Steven J.E. Wilton
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 1998
Abstract
It has become clear that large embedded configurable memory arrays
will be essential in future FPGAs. Embedded arrays provide high-density
high-speed implementations of the storage parts of circuits. Unfortunately,
they require the FPGA vendor to partition the device into memory and logic
resources at manufacture-time. This leads to a waste of chip area for
customers that do not use all of the storage provided. This chip area need
not be wasted, and can in fact be used very efficiently, if the arrays are
configured as large multi-output ROMs, and used to implement logic.
In order to efficiently use the embedded arrays in this way, a technology
mapping algorithm that identifies parts of circuits that can be efficiently
mapped to an embedded array is required. In this paper, we describe such an
algorithm. The new tool, called SMAP, packs as much circuit information as
possible into the available memory arrays, and maps the rest of the circuit
into four-input lookup-tables. On a set of 29 sequential and combinational
benchmarks, the tool is able to map, on average, 60 4-LUTs into a single
2-Kbit memory array. If there are 16 arrays available, it can map,
on average, 358 4-LUTs to the 16 arrays.
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