FPGA Clock Network Architecture: Flexibility vs. Area and Power
Julien Lamoureux and Steven J.E. Wilton
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2006
Abstract
This paper examines the tradeoffs between flexibility, area, and
power dissipation of programmable clock networks for Field-
Programmable Gate Arrays (FPGA’s). The paper begins by describing
a parameterized clock network model that describes a
broad range of programmable clock network architectures. Specifically,
the model supports architectures with multiple local and
global clock domains and varying amounts of flexibility at various
levels of the clock network. Using the model, the architectural
parameters that control the flexibility of the clock network are
varied to determine the cost of this flexibility in terms of area and
power dissipation. From these experiments, the study finds that
area and power costs are highest for networks with flexibility
close to the logic blocks. Furthermore, it found that clock networks
with local clock domains have little overhead and are significantly
more efficient than clock networks without local clock
domains for applications with multiple clocks.
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