Detailed Routing Architectures for Embedded Programmable Logic IP Cores
Peter Hallschmid and Steven J.E. Wilton
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2001
Abstract
As the complexity of integrated circuits increases,
the ability to make post-fabrication changes to fixed ASIC chips
will become more and more attractive. This ability can be
realized using programmable logic cores. These cores are blocks
of programmable logic that can be embedded into a fixed-function
ASIC or custom chip. Such cores differ from stand-alone FPGAs
in that they can take on a variety of shapes and sizes. With
this in mind, we investigate the detailed routing characteristics
of rectangular programmable logic cores. We quantify the effects
of having different x and y channel capacities, and show that
the optimum ratio between the x and y channel widths for a
rectangular core is between 1.2 and 1.5. We also present
a new switch block family optimized for rectangular cores.
Compared to a simple extension of an existing switch block,
our new architecture leads to an 8.7% improvement in density
with little effect on speed. Finally, we show that if the
channel widths and switch block are chosen carefully, the
penalty for using a rectangular core (compared to a square
core with the same logic capacity) is small; for a core
with an aspect ratio of 2:1, the area penalty is
1.6% and the speed penalty is 1.1%.
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