Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs
C.H. Ho, P.H.W. Leong, W. Luk, S.J.E. Wilton, S. Lopez-Buedo
IEEE Symposium on Field-Programmable Custom Computing Machines, April 2006
Abstract
Embedded elements, such as block multipliers, are increasingly
used in advanced field programmable gate array
(FPGA) devices to improve efficiency in speed, area and
power consumption. A methodology is described for assessing
the impact of such embedded elements on efficiency.
The methodology involves creating dummy elements, called
Virtual Embedded blocks (VEBs), in the FPGA to model
the size, position and delay of the embedded elements. The
standard design flow offered by FPGA and CAD vendors
can be used for mapping, placement, routing and retiming
of designs with VEBs. The speed and resource utilisation of
the resulting designs can then be inferred using the FPGA
vendor's timing analysis tools. We illustrate the application
of this methodology to the evaluation of various schemes
of involving embedded elements that support floating-point
computations.
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