Embedded Configurable Memories in FPGAs:

Steve Oldridge, Ernie Lin, Jason Clifford, William Ho, Steve Wilton, Jonathan Rose, Zvonko Vranesic

In a current project, we are investigating the architectures and algorithms of FPGAs with on-chip storage. The constant improvement in FPGA and process technology is changing the way FPGAs are used and designed. In the past, the relative low capacities of these devices have limited their use to small logic subcircuits, but as FPGAs grow, designers are able to use them to implement much larger systems. These larger systems look significantly different than small logic subcircuits; one of the key differences is that these systems often contain memory. Memory, therefore, will be a crucial component of future FPGAs.

One of the challenges when embedding memory arrays onto an FPGA is to provide enough interconnect between the memory arrays and the logic resources. The design of a good memory/logic interface is critical. Since memory access time is often the performance bottleneck in many systems, it is crucial that the memory/logic interface provides a flexible high-speed link between logic and memory. If the interface is not flexible enough, many circuits will be unroutable, while if it is too flexible, it will be slower and consume more chip area than is necessary. Much of our research has focused on the design of a good memory/logic interface. We concentrate on two issues: how flexible the interconnect must be, and how the interconnect can be enhanced by providing efficient connections between the memory arrays themselves.

We are also investigating an alternative architecture, in which shallow wide memories are provided by allowing the user to write and read the configuration memory in unused switch blocks. Implementing this technique on a 100 x 100 logic block FPGA with 128 tracks per channel gives a total of 9.46 Megabits of memory which can be accessed using an arbitrary word width. The circuitry to provide access to the configuration bits in this way consists of 3.58 transistors per bit, and results in a routing speed degradation of 11.6%

The 1998 Douglas R. Colton Medal for Research Excellence was received for a portion of this project.

Funding for this project has been provided by Cypress Semiconductor and the B.C. Advanced Systems Institute.

• S.W. Oldridge and S.J.E. Wilton, "A Novel FPGA Architecture Supporting Wide, Shallow Memories", in IEEE Transactions on Very-Large Scale Integration (VLSI) Systems, Vol. 13, Issue 6, June 2005, pp. 758-762.
• S.J.E. Wilton, C.W. Jones, J. Lamoureux, "An Embedded Flexible Content-Addressable Memory Core for Inclusion in a Field-Programmable Gate Array", in the IEEE International Symposium on Circuits and Systems, Vancouver, B.C., May 2004, Vol. II, pp. 885-888. [abstract] [pdf]
• S.W. Oldridge, S.J.E. Wilton, "Placement and Routing for FPGA Architectures Containing Wide Shallow Memories", in the IEEE International Conference on Field-Programmable Technology, Tokyo, Japan, December 2003, pp. 154-161.
• C.J. Jones, S.J.E. Wilton, "Content-addressable Memory with Cascaded Match, Read and Write Logic in a Programmable Logic Device", U.S. Patent 6,622,204. Issued Sept. 16, 2003.
• S.J.E. Wilton, ``Implementing Logic in FPGA Memory Arrays: Heterogeneous Memory Architectures'', to appear in IEEE International Conference on Field-Programmable Technology, December 2002.
• S.W. Oldridge, ``A Novel FPGA Supporting Wide Shallow Memories'', M.A.Sc. Thesis, April 2002. [abstract] [pdf]
• E. Lin, S.J.E. Wilton, ``The Architecture of Dual-Mode FPGA Embedded System Blocks'', to appear in IEEE Custom Integrated Circuits Conference, May 2002.
• E. Lin, ``Product Term Mode Embedded Memory Arrays: Architectures and Algorithms'', M.A.Sc. Thesis, September 2001. [abstract] [pdf]
• E. Lin, S.J.E. Wilton, ``Macrocell Architectures for Product Term Embedded Memory Arrays'', in the 11th International Conference on Field-Programmable Logic and Applications, Aug 2001. [abstract]
• S.W. Oldridge, S.J.E. Wilton, ``A Novel FPGA Architecture Supporting Wide Shallow Memories'', in the IEEE Custom Integrated Circuits Conference, San Diego, CA, May 2001, pp. 75-78. [abstract] [pdf]
• Jason P. Clifford, Steven J.E. Wilton, ``Architecture of Cluster-Based FPGAs with Memory'', in the IEEE Custom Integrated Circuits Conference, Orlando, FL, May 1999, pp. 131-134. [abstract] [pdf]
• William K.C. Ho, Steven J.E. Wilton, ``Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays'', in International Workshop on Field Programmable Logic and Applications , Aug. 1999. [abstract] [pdf]
• S.J.E. Wilton, ``FPGA Embedded Memory Architectures: Recent Research Results'', in IEEE Pacific Rim Conference on Communications, Computers and Signal Processing , Aug. 1999. [abstract] [pdf]
• S.J.E. Wilton, J. Rose, Z.G. Vranesic, ``The Memory/Logic Interface in FPGAs with Large Embedded Memory Arrays'', IEEE Transactions on Very-Large Scale Integration Systems , vol. 7, no. 1, March 1999. [abstract]
• S.J.E. Wilton, J. Rose, Z.G. Vranesic ``Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays'', ACM/SIGDA International Symposium on Field-Programmable Gate Arrays , pp. 10-16, Feb. 1997. [abstract] [postscript]
• S.J.E. Wilton, J. Rose, Z.G. Vranesic ``Memory/Logic Interconnect Flexibility in FPGAs with Large Embedded Memory Arrays,'' IEEE Custom Integrated Circuits Conference , May 1996. [abstract] [pdf] [html]
• Steven J.E. Wilton, ``Architecture and Algorithms for Field-Programmable Gate Arrays with Embedded Memory,'' PhD thesis, University of Toronto, 1997. [abstract] [postscript] [pdf]

Back to Steve Wilton's Home Page