Brad Quinton, Mark Greenstreet, Steve Wilton
Advances in integrated circuit (IC) technology have made possible the integration of a large number of functional blocks on a single chip. There are many challenges associated with this high level of integration. One of these challenges is ensuring that the IC design is functionally correct. Although prefabrication simulation is used to help ensure that the IC performs as desired, the complexity of modern ICs prevents exhaustive verification. Design errors (bugs) are often found post-fabrication. For complex ICs, the process of verifying and debugging new devices is a significant cost and time investment. As the level of IC integration continues to rise, this problem will be exasperated as more functionality is combined into a single "black-box" that must be tested using only the external chip interfaces.
In this work, we show that programmable logic cores (PLCs) embedded on fixed-function ICs offer a unique opportunity to address this problem. During the post-fabrication verification of ICs, a flexible network is used to provide relevant signals from within the fixed-function IC to the programmable logic core; the programmable logic core is then be used to monitor these signals, and return information about these signals to the verifier (possibly in real-time). In more complicated cases the verifier can override the internal signal to observe the effect on the output of the IC.
Embedding programmable logic cores on fixed function SoCs is not new. In previous designs, however, the purpose of the programmable logic core is to provide post-fabrication flexibility for the design itself. Using this approach the parts of the design that are expected to change are mapped to the programmable logic core. Then, if requirements change post-fabrication, these changes can hopefully be incorporated into the programmable logic portion of the chip. Our approach is different in that our programmable logic core is not used to implement part of the design. Instead, we use the programmable logic core solely to implement debugging circuitry that will be used to debug the fixed-function chip. This unique use of a programmable logic core requires a unique flexible network, as well as unique interface circuitry. Our debugging architecture, which contains the programmable logic core as well as the network and interface circuitry, is the focus of this work.
The post manufacturing re-configurability of the network and programmable logic core is a key aspect of the technique. During post-fabrication verification, the region of the circuit being debugged may change over time, and in any case, is not likely predictable during design time. The flexible network allows the verifier to select the internal signals that are of interest for any given test, and the programmable logic core provides a means to process these signals in a manner that depends on the debugging task being performed.
The ability to easily verify ICs in this way provides a number of benefits: 1) Reduced time-to market because of an increased ability to isolate and understand unexpected behaviours, 2) Decreased resources required for post-manufacturing verification because of an increase in the functional coverage of a given test, 3) Elimination of design revisions caused when one design error hides a second error, 4) Increased customer satisfaction because of enhanced ability to provide "workarounds" to known bugs.