Fall 2010: Thrusday's, 4pm to 4:45pm in KAIS 4018

October 20, 2010

Ahn et al., Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks, micro 2010

October 20, 2010

Chung et al., ASF: AMD64 Extension for Lock-free Data Structures and Transactional Memory, micro 2010

September 30, 2010

Awasthi et al., Handling the Problems and Opportunities Posed by Multiple On-Chip Memory Controllers, PACT 2010

September 23, 2010

Raman et al., Speculative Parallelization Using Software Multi-threaded Transactions, ASPLOS 2010

September 9, 2010

Blake et al., Evolution of thread-level parallelism in desktop applications, ISCA 2010

September 1, 2010

Suleman et al., Data Marshaling for Multi-core Architectures, ISCA 2010

Summer 2010: Tuesday's, 10:00am to 12pm in KAIS 4018

August 25, 2010

Watanabe et al., WiDGET: Wisconsin Decoupled Grid Execution Tiles, ISCA 2010

August 18, 2010

Yang et al., A GPGPU Compiler for Memory Optimization and Parallelism Management, PLDI 2010

August 12, 2010

Hong et al., An integrated GPU power and performance model, ISCA 2010

August 4, 2010

Hameed et al., Understanding Sources of Inefficiency in General-Purpose Chips, ISCA 2010

July 28, 2010

Reddi et al., Web Search Using Mobile Cores: Quantifying and Mitigating the Price of Effciency, ISCA 2010

July 21, 2010

Stuecheli et al., The virtual write queue: coordinating DRAM and last-level cache policies, ISCA 2010

July 14, 2010

Blundell et al., RETCON: Transactional Repair without Replay, ISCA 2010

July 7, 2010

Hormati et al., MacroSS: Macro-SIMDization of Streaming Applications, ASPLOS 2010

June 30, 2010

Gelado et al., An asymmetric distributed shared memory model for heterogeneous parallel systems ASPLOS 2010

June 25, 2010

Eyerman et al., Modeling Critical Sections in Amdahls Law and its Implications for Multicore Design, ISCA 2010

June 15, 2010

Lee et al., Dynamically Weaving Threads Together for Efficient, Adaptive Parallel Applications, ISCA 2010

June 8, 2010

Das et al., Argia: Exploiting Packet Latency Slack in On-Chip Networks, ISCA 2010

May 26, 2010

Kelm et al., Cohesion*: A Hybrid Memory Model for Accelerator, ISCA 2010

May 18, 2010

Meng et al., Dynamic Warp Subdivision for Integrated Branch and Memory Divergence Tolerance, ISCA 2010

Spring 2010: Tuesday's, 4pm to 6pm in KAIS 4018

March 16, 2010

Hoberock et al., Stream compaction for deferred shading, HPG 2009

March 9, 2010

Moscibroda et al., A Case for Bufferless Routing in On-Chip Networks, ISCA 2009
Kachris et al., Configurable Transactional Memory, FCCM 2007
Chang et al., Automating post-silicon debugging and repair, ICCAD 2007
Lakshminarayana et al., Age based scheduling for asymmetric multiprocessors SC 2009

March 2, 2010

Lakshminarayana et al., Effect of Instruction Fetch and Memory Scheduling on GPU Performance, HPCA/PPoPP 2010
Briggs et al., Improvements to graph coloring register allocation, TOPLAS 1994
Sanchez et al., Flexible Architectural Support for Fine-Grain Scheduling, ASPLOS 2010
Raman et al., Speculative Parallelization Using Software Multi-threaded Transactions, ASPLOS 2010

February 1, 2010

Ebrahimi et al., Coordinated Control of Multiple Prefetchers in Multi-Core Systems, MICRO-42
Romanescu et al., Unified Instruction/Translation/Data (UNITD) Coherence: One Protocol to Rule Them All, HPCA 2010
Mytkowicz et al., Producing Wrong Data Without Doing Anything Obviously Wrong!, ASPLOS 2009

January 26, 2010

Kim et al., Low-Cost Router Microarchitecture, MICRO-42
Garg et al., A performance-correctness explicitly-decoupled architecture, MICRO-41
Kelm et al., A Task-centric Memory Model for Scalable Accelerator Architectures, PACT 2009
Hofmann et al., Maximal Benefit from a Minimal HTM, ASPLOS 2009

January 19, 2010

Das et al., Application-Aware Prioritization Mechanisms for On-Chip Networks, MICRO-42
Doudalis et al., HARE: Hardware Assisted Reverse Execution, HPCA 2010
Jafri et al., LiteTM: Reducing Transactional State Overhead, HPCA 2010