Summer 2008: Friday's, 12 noon to 2pm in KAIS 4018
July 25, 2008
Agarwal et al., Fetch-Criticality Reduction through Control Independence, ISCA 2008
Chu et al., Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures, MICRO 2007
July 18, 2008
Kumar and Huggahalli, Impact of Cache Coherence Protocols on the Processing of Network Traffic, MICRO 2007
Montesinos et al., DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently, ISCA 2008
July 11, 2008
Lee et al., Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks, ISCA 2008
Kgil et al., Improving NAND Flash Based Disk Caches, ISCA 2008
July 4, 2008
Loh, 3D-Stacked Memory Architectures for Multi-Core Processors, ISCA 2008
Vantrease et al., Corona: System Implications of Emerging Nanophotonic Technology, ISCA 2008
No reading group June 20&27 due to ISCA 2008
June 13, 2008
Jerger et al., Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support, ISCA 2008.
Thoziyoor et al., A Comprehensive Memory Modeling Tool and its Application to the Design and Analysis of Future Memory Hierarchies, ISCA 2008
June 6, 2008
Lindholm et al., NVIDIA Tesla: A Unified Graphics and Computing Architecture, IEEE Micro Mar/Apr 2008.
Kumar et al., Atomic Vector Operations on Chip Multiprocessors, ISCA 2008.
May 30, 2008
Gelado et al., CUBA: An Architecture for Efficient CPU/Co-processor Data Communication, ICS 2008.
Tseng and Patt, Achieving Out-of-Order Performance with Almost In-Order Complexity, ISCA 2008.
Spring 2008: Friday's, 12 noon to 2pm in KAIS 4018
April 18, 2008
Fung et al. (draft of journal submission)
March 21, 2008
Tiwari et al., ReCycle: pipeline adaptation to tolerate process variation, ISCA 2007.
March 7, 2008
Bhargava et al., Accelerating Two-Dimensional Page Walks for Virtualized Systems, ASPLOS 2008.
Feb. 29, 2008
Burcea et al., Predictor Virtualization, ASPLOS 2008.
Feb 15, 2008
Hu et al., Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior, ISCA 2002.
Feb 8, 2008
Basu et al., Scavenger: A New Last Level Cache Architecture with Global Block Priority, MICRO 2007.
Feb 1, 2008
Ryoo et al., Program Optimization Space Pruning for a Multithreaded GPU, CGO 2008.
Jan 25, 2008
Yeh et al., The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration, MICRO 2007.
Jan 18, 2008
Kim et al., Composable Lightweight Processors, MICRO 2007.