Fall 2007: Thursdays, 12 noon to 2pm in KAIS 4018 (papers posted ~noon Sundays)

November 15, 2007

Hochstein et al., Parallel Programmer Productivity: A Case Study of Novice Parallel Programmers, SC'05.

October 25, 2007

Ozdemir, et al., Yield-Aware Cache Architectures, MICRO 2006.

October 18, 2007

Ferrante et al., The program dependence graph and its use in optimization, ACM Trans. Prog. Lang. and Sys., 1987.

October 11, 2007

Bridges et al., Revisiting the Sequential Programming Model for Multi-Core", MICRO 2007.

September 27, 2007

Igehy et al., Prefetching in a Texture Cache Architecture, Graphics Hardware 1998.

September 20, 2007

Bernick et al., Nonstop Advanced Architecture, DSN 2005.

September 13, 2007

Kumar et al., Core Architecture Optimization for Heterogeneous Chip Multiprocessors, PACT 2006.
Mesnier et al., Modeling the Relative Fitness of Storage, SIGMETRICS 2007.

September 6, 2007

Ohsawa, et al., Pinot: Speculative Multi-threading Processor Architecture Exploiting Parallelism over a Wide Range of Granularities, MICRO 2005
Marty et al., Coherence Ordering for Ring-based Chip Multiprocessors, MICRO 2006

Summer 2007: Thursdays, 12 noon to 2pm in KAIS 4018 (papers posted ~4pm Wednesdays)

August 30, 2007

Qureshi et al., Line Distillation: Increasing Cache Capacity By Filtering Unused Words in Cache Lines, HPCA 2007
Reddy et al., Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance, ASPLOS 2006

August 23, 2007

Ipek et al., Core Fusion: Accommodating Software Diversity in Chip Multiprocessors, ISCA 2007
Eisley et al., In-Network Cache Coherence, MICRO 2006

August 16, 2007

Etsion and Feitelson, L1 Cache Filtering Through Random Selection of Memory References, PACT 2007
Patwardhan et al., A defect tolerant self-organizing nanoscale SIMD architecture, ASPLOS 2006

August 9, 2007

Cantin et al., Stealth prefetching, ASPLOS 2006
Sampson et al., Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers, MICRO 2006

August 2, 2007

Solar-Lezama et al., Combinatorial Sketching for Finite Programs, ASPLOS 2006
Mysore et al., Introspective 3D Chips, ASPLOS 2006

July 26, 2007

Srinath et al., Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers, HPCA 2007
Tuck et al., Scalable Cache Miss Handling for High Memory-Level Parallelism, MICRO 2006

July 19, 2007

Sankaralingam et al., Distributed Microarchitectural Protocols in the TRIPS Prototype Processor, MICRO 2006
Shin et al., Introducing Control Flow into Vectorized Code, PACT 2007

July 12, 2007

Subramanian et al. Adaptive Caches: Effective Shaping of Cache Behavior to Workloads, MICRO 2006
Agarwal et al., Exploiting Postdominance for Speculative Parallelization, HPCA 2007

July 5, 2007

Sarangi et al., Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware, MICRO 2006
Kirman et al., Leveraging Optical Technology in Future Bus-based Chip Multiprocessors, MICRO 2006

June 27, 2007

Wenisch et al., Mechanisms for Store-wait-free Multiprocessors, ISCA 2007
Ceze et al., BulkSC: Bulk Enforcement of Sequential Consistency, ISCA 2007

June 14, 2007

Nesbit et al., Virtual Private Caches, ISCA 2007
Chi et al., Tailoring Quantum Architectures to Implementation Style: A Quantum Computer for Mobile and Persistent Qubits, ISCA 2007

June 7, 2007

D.E. Shaw et al., Anton, a Special-Purpose Machine for Molecular Dynamics Simulation, ISCA 2007.
S. Kumar et al, Carbon: Architectural Support for Fine-Grained Parallelism on Chip Multiprocessors, ISCA 2007.

May 31, 2007

W. Zhu et al., Synchronization State Buffer: Supporting Efficient Fine-Grain Synchronization on Many-Core Architectures, ISCA 2007
P.G. Sassone et al., Matrix Scheduler Reloaded, ISCA 2007.

May 24, 2007

A. McDonald et al., Architectural Semantics for Practical Transactional Memory, ISCA 2006
F. Blagojevic et al., Dynamic Multigrain Parallelization on the Cell Broadband Engine, PPoPP 2007

May 17, 2007

A. Kumar et al., Express Virtual Channels: Towards the Ideal Interconnection Fabric, ISCA 2007.
J. Leverich et al., Comparing Memory Systems for Chip Multiprocessors, ISCA 2007.